Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: fft Download
 Description: Function: base 8 implement 64-point FFT processor (twice 8:00 FFT calculation, using the base 8 of 64 points) Description: The hardware configuration consists of six parts, namely, an input module, 8-point FFT module, multiplication module, order adjustment module, the output module and total control module. Among them, the 64 data input module is the main function of the serial input classification, divided into eight lots, each 8 inputs and 8-point FFT module calculation. 8:00 FFT module: FFT is a fast algorithm for DFT, when a large number of points, you can greatly reduce the amount of computation of the DFT. FFT algorithm commonly used mainly two were decimated by time FFT algorithm (DIT-FFT) algorithms and FFT decimation in frequency (DIF-FFT). In our design, we have adopted is based on the frequency of lottery 8:00 FFT algorithm. Multiplication module: Since rotational symmetry factor, you only need to generate 8 constant factor. But it will reuse some of the units, which af
 Downloaders recently: [More information of uploader 李圣华]
 To Search:
File list (Check if you may need any files):
 

rtl
...\const_unit.v
...\ctrl_count.v
...\fft_8.v
...\fft_top.v
...\input_unit.v
...\minus.v
...\multiplier.v
...\output_unit.v
...\rb.v
...\shuffer_in.v
...\shuffer_out.v
...\sqr2.v
...\td0.v
...\td1.v
...\td1_im.v
...\td1_re.v
...\td2.v
...\td2_im.v
...\td2_re.v
...\td3.v
...\td3_im.v
...\td3_re.v
...\td4.v
...\td4_im.v
...\td4_re.v
...\td5.v
...\td5_im.v
...\td5_re.v
...\td6.v
...\td6_im.v
...\td6_re.v
...\td7.v
...\td7_im.v
...\td7_re.v
...\td8.v
...\td8_im.v
...\td8_re.v
    

CodeBus www.codebus.net