Verilog语言写的SPI接口\rtl_spi\spi.v
......................\.......\spi_bitcounter.v
......................\.......\spi_bitcounter_rtl.v
......................\.......\spi_bytecounter.v
......................\.......\spi_bytecounter_rtl.v
......................\.......\spi_clkdiv_count.v
......................\.......\spi_clkdiv_count_rtl.v
......................\.......\spi_clock_gen.v
......................\.......\spi_comp3_ge.v
......................\.......\spi_comp3_ge_rtl.v
......................\.......\spi_comp3_se.v
......................\.......\spi_comp3_se_rtl.v
......................\.......\spi_control.v
......................\.......\spi_core.v
......................\.......\spi_cs_cnt.v
......................\.......\spi_cs_cnt_rtl.v
......................\.......\spi_equal3.v
......................\.......\spi_equal3_rtl.v
......................\.......\spi_fifo.v
......................\.......\spi_it.v
......................\.......\spi_map.v
......................\.......\spi_page_cnt.v
......................\.......\spi_page_cnt_rtl.v
......................\.......\spi_regs.v
......................\.......\spi_tx_rx.v
......................\.......\spi_waitcounter.v
......................\.......\spi_waitcounter_rtl.v
......................\rtl_spi
Verilog语言写的SPI接口