- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 1kb
- Update:
- 2014-03-03
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- 0 Times
- Uploaded by:
- 文辺
Description: Ideal state of four traffic lights design, CPLD/FPGA-driven, time can be changed.
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jiaotongdeng.vhd