Synplify_Pro
............\ALU_Syn_2.prd
............\ALU_Syn_2.prj
............\ALU_Syn_demo.prd
............\ALU_Syn_demo.prj
............\ALU_Syn_demo.sdc
............\Mix_src.prd
............\Mix_src_vhdl.prd
............\Mix_src_vhdl.prj
............\Mix_src_vlog.prd
............\Mix_src_vlog.prj
............\MyWorkspace.prd
............\MyWorkspace.prj
............\rev_1
............\.....\ALU.fse
............\.....\ALU.srd
............\.....\ALU.srm
............\.....\ALU.srr
............\.....\ALU.srs
............\.....\ALU.sxr
............\.....\ALU.tcl
............\.....\ALU.tlg
............\.....\ALU.vqm
............\.....\ALU.xrf
............\.....\ALU_cons.tcl
............\.....\ALU_rm.tcl
............\.....\AutoConstraint_alu.sdc
............\.....\HDL_DEMO.fse
............\.....\HDL_DEMO.srd
............\.....\HDL_DEMO.srm
............\.....\HDL_DEMO.srr
............\.....\HDL_DEMO.srs
............\.....\HDL_DEMO.sxr
............\.....\HDL_DEMO.ta
............\.....\HDL_DEMO.taq
............\.....\HDL_DEMO.tcl
............\.....\HDL_DEMO.tlg
............\.....\HDL_DEMO.vqm
............\.....\HDL_DEMO.xrf
............\.....\HDL_DEMO_cons.tcl
............\.....\HDL_DEMO_rm.tcl
............\.....\HDL_DEMO_ta.srm
............\.....\fsmviewer.fsm
............\.....\syntmp
............\.....\......\ALU.plg
............\.....\......\HDL_DEMO.plg
............\rev_2
............\.....\.recordref
............\.....\AutoConstraint_top.sdc
............\.....\layer0.tlg
............\.....\layer1.tlg
............\.....\layer2.tlg
............\.....\syntmp
............\.....\......\top.plg
............\.....\top.fse
............\.....\top.srd
............\.....\top.srm
............\.....\top.srr
............\.....\top.srs
............\.....\top.sxr
............\.....\top.tcl
............\.....\top.vqm
............\.....\top.xrf
............\.....\top_cons.tcl
............\.....\top_rm.tcl
............\rev_3
............\.....\.recordref
............\.....\layer0.tlg
............\.....\layer1.tlg
............\.....\layer2.tlg
............\.....\syntmp
............\.....\......\mux.plg
............\.....\......\rotate.plg
............\.....\......\top.plg
............\.....\......\top1.plg
............\.....\top1.fse
............\.....\top1.srd
............\.....\top1.srm
............\.....\top1.srr
............\.....\top1.srs
............\.....\top1.sxr
............\.....\top1.tcl
............\.....\top1.vqm
............\.....\top1.xrf
............\.....\top1_cons.tcl
............\.....\top1_rm.tcl
............\source
............\......\VHDL
............\......\....\ALU.VHD
............\......\....\HDL_DEMO.VHD
............\......\mixed
............\......\.....\verilog
............\......\.....\.......\mux.vhd
............\......\.....\.......\mux21.v
............\......\.....\.......\reg8.vhd
............\......\.....\.......\rotate.vhd
............\......\.....\.......\top.v
............\......\.....\vhdl
............\......\.....\....\mux.v
............\......\.....\....\mux21.vhd