Description: Gray code based on FIFO IP core, debugging can be used for communication queue transmission interface.
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File list (Check if you may need any files):
generic_fifos
.............\branches
.............\tags
.............\....\start
.............\....\.....\bench
.............\....\.....\.....\verilog
.............\....\.....\.....\.......\test_bench_top.v
.............\....\.....\doc
.............\....\.....\...\README.txt
.............\....\.....\rtl
.............\....\.....\...\verilog
.............\....\.....\...\.......\generic_fifo_dc.v
.............\....\.....\...\.......\generic_fifo_sc_a.v
.............\....\.....\...\.......\generic_fifo_sc_b.v
.............\....\.....\...\.......\timescale.v
.............\....\.....\sim
.............\....\.....\...\rtl_sim
.............\....\.....\...\.......\bin
.............\....\.....\...\.......\...\Makefile
.............\....\.....\...\.......\run
.............\....\.....\...\.......\...\waves
.............\....\.....\...\.......\...\.....\waves.do
.............\trunk
.............\.....\bench
.............\.....\.....\verilog
.............\.....\.....\.......\test_bench_top.v
.............\.....\doc
.............\.....\...\README.txt
.............\.....\rtl
.............\.....\...\verilog
.............\.....\...\.......\generic_fifo_dc.v
.............\.....\...\.......\generic_fifo_dc_gray.v
.............\.....\...\.......\generic_fifo_lfsr.v
.............\.....\...\.......\generic_fifo_sc_a.v
.............\.....\...\.......\generic_fifo_sc_b.v
.............\.....\...\.......\lfsr.v
.............\.....\...\.......\timescale.v
.............\.....\sim
.............\.....\...\rtl_sim
.............\.....\...\.......\bin
.............\.....\...\.......\...\Makefile
.............\.....\...\.......\run
.............\.....\...\.......\...\waves
.............\.....\...\.......\...\.....\waves.do
.............\web_uploads
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