- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 366kb
- Update:
- 2013-11-21
- Downloads:
- 0 Times
- Uploaded by:
- a
Description: Perform basic gate "and" operation. There are several input, there is only one output. When all the input for the "1" at ordinary times at the same time, the output for a "1" level, otherwise output for the "0" level.
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File list (Check if you may need any files):
Project\and_gate.asm.rpt
.......\and_gate.done
.......\and_gate.dpf
.......\and_gate.fit.rpt
.......\and_gate.fit.smsg
.......\and_gate.fit.summary
.......\and_gate.flow.rpt
.......\and_gate.map.rpt
.......\and_gate.map.summary
.......\and_gate.pin
.......\and_gate.pof
.......\and_gate.qpf
.......\and_gate.qsf
.......\and_gate.sof
.......\and_gate.tan.rpt
.......\and_gate.tan.summary
.......\db\and_gate.asm.qmsg
.......\..\and_gate.asm_labs.ddb
.......\..\and_gate.cbx.xml
.......\..\and_gate.cmp.bpm
.......\..\and_gate.cmp.cdb
.......\..\and_gate.cmp.ecobp
.......\..\and_gate.cmp.hdb
.......\..\and_gate.cmp.logdb
.......\..\and_gate.cmp.rdb
.......\..\and_gate.cmp.tdb
.......\..\and_gate.cmp0.ddb
.......\..\and_gate.cmp2.ddb
.......\..\and_gate.cmp_bb.cdb
.......\..\and_gate.cmp_bb.hdb
.......\..\and_gate.cmp_bb.logdb
.......\..\and_gate.cmp_bb.rcf
.......\..\and_gate.dbp
.......\..\and_gate.db_info
.......\..\and_gate.eco.cdb
.......\..\and_gate.fit.qmsg
.......\..\and_gate.hier_info
.......\..\and_gate.hif
.......\..\and_gate.map.bpm
.......\..\and_gate.map.cdb
.......\..\and_gate.map.ecobp
.......\..\and_gate.map.hdb
.......\..\and_gate.map.logdb
.......\..\and_gate.map.qmsg
.......\..\and_gate.map_bb.cdb
.......\..\and_gate.map_bb.hdb
.......\..\and_gate.map_bb.logdb
.......\..\and_gate.pre_map.cdb
.......\..\and_gate.pre_map.hdb
.......\..\and_gate.psp
.......\..\and_gate.pss
.......\..\and_gate.rpp.qmsg
.......\..\and_gate.rtlv.hdb
.......\..\and_gate.rtlv_sg.cdb
.......\..\and_gate.rtlv_sg_swap.cdb
.......\..\and_gate.sgate.rvd
.......\..\and_gate.sgate_sm.rvd
.......\..\and_gate.sgdiff.cdb
.......\..\and_gate.sgdiff.hdb
.......\..\and_gate.signalprobe.cdb
.......\..\and_gate.sld_design_entry.sci
.......\..\and_gate.sld_design_entry_dsc.sci
.......\..\and_gate.syn_hier_info
.......\..\and_gate.tan.qmsg
.......\..\and_gate.tis_db_list.ddb
.......\..\prev_cmp_and_gate.map.qmsg
.......\..\prev_cmp_and_gate.qmsg
.......\Project\and_gate.asm.rpt
.......\.......\and_gate.done
.......\.......\and_gate.dpf
.......\.......\and_gate.fit.rpt
.......\.......\and_gate.fit.smsg
.......\.......\and_gate.fit.summary
.......\.......\and_gate.flow.rpt
.......\.......\and_gate.map.rpt
.......\.......\and_gate.map.summary
.......\.......\and_gate.pin
.......\.......\and_gate.pof
.......\.......\and_gate.qpf
.......\.......\and_gate.qsf
.......\.......\and_gate.sof
.......\.......\and_gate.tan.rpt
.......\.......\and_gate.tan.summary
.......\.......\db\and_gate.asm.qmsg
.......\.......\..\and_gate.asm_labs.ddb
.......\.......\..\and_gate.cbx.xml
.......\.......\..\and_gate.cmp.bpm
.......\.......\..\and_gate.cmp.cdb
.......\.......\..\and_gate.cmp.ecobp
.......\.......\..\and_gate.cmp.hdb
.......\.......\..\and_gate.cmp.logdb
.......\.......\..\and_gate.cmp.rdb
.......\.......\..\and_gate.cmp.tdb
.......\.......\..\and_gate.cmp0.ddb
.......\.......\..\and_gate.cmp2.ddb
.......\.......\..\and_gate.cmp_bb.cdb
.......\.......\..\and_gate.cmp_bb.hdb
.......\.......\..\and_gate.cmp_bb.logdb
.......\.......\..\and_gate.cmp_bb.rcf
.......\.......\..\and_gate.dbp
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