TB\alu.v
..\basic.asm
..\BASIC.HEX
..\basic.rom
..\CPU.cr.mti
..\CPU.mpf
..\cpu.v
..\dds.asm
..\DDS.HEX
..\dds.rom
..\dram.v
..\exp.v
..\exp.vPreview
..\hex2v.c
..\idec.v
..\pram.v
..\regs.v
..\risc8.vcd
..\runit
..\sindata.c
..\sindata.hex
..\tcl_stacktrace.txt
..\test.v
..\test.v.bak
..\test.v~
..\vsim.wlf
..\work\alu\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\cpu\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\dram\verilog.asm
..\....\....\_primary.dat
..\....\....\_primary.vhd
..\....\exp\verilog.asm
..\....\...\_primary.dat
..\....\...\_primary.vhd
..\....\idec\verilog.asm
..\....\....\_primary.dat
..\....\....\_primary.vhd
..\....\pram\verilog.asm
..\....\....\_primary.dat
..\....\....\_primary.vhd
..\....\regs\verilog.asm
..\....\....\_primary.dat
..\....\....\_primary.vhd
..\....\test\verilog.asm
..\....\....\_primary.dat
..\....\....\_primary.vhd
..\....\_info
..\....\alu
..\....\cpu
..\....\dram
..\....\exp
..\....\idec
..\....\pram
..\....\regs
..\....\test
..\work
TB