- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 79kb
- Update:
- 2013-03-20
- Downloads:
- 0 Times
- Uploaded by:
- ww
Description: The AD acquisition, DDC, FIRD etc. filtering procedures, adc lvds interface
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src_adc\adc_if_subtop.vhd
.......\ddc_subtop.vhd
.......\ddr3_ctl_bot_if.vhd
.......\ddr3_ctl_top_if.vhd
.......\ddr3_top.vhd
.......\dma_ctl.vhd
.......\ev10aq190_spi_cfg.vhd
.......\fiber_top.vhd
.......\..r\ddc_subtop.vhd
.......\...\fir_16p.vhd
.......\...\fir_ip.vhd
.......\fir_16p.vhd
.......\fir_ip.vhd
.......\frame_generate.vhd
.......\global_pll_top.vhd
.......\global_pll_top.vhd.bak
.......\h014_adc_top - 副本.vhd
.......\h014_adc_top.vhd
.......\h014_adc_top.vhd.bak
.......\Package_QL5064.vhd
.......\ql5064_v3_if_top.vhd
.......\reg_ctl.vhd
.......\sl2_12x_if.vhd
.......\sl2_8x_if - 副本.vhd
.......\sl2_8x_if.vhd
.......\standard_data.vhd
.......\trigger_module_top.vhd
.......\fir
src_adc
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