- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 59kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- 张永满
Description: Responder timer input is grab the signal, the clock signal and the host signal. When the host signal (' 0 ' ), the clock signal timing, grab began after the effective timing. First 48Mhz clock divider for a 1hz The time signal, to grab the signal (' 0 ' ), the time to signal (sjd) assignment is invalid ' 1' , and by the the 1hz time signal output time display seven segment decoded signal: After a cycle, they put a countdown time minus one and seven-segment decoder output shown in the corresponding time values. After 5 seconds (4,3, ....., 0), represents the time, the time signal (SJD) assignment is valid (' 0 ' ).
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2基于FPGA的抢答定时电路设计及仿真.docx
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