Description: • LFSR uses global clock
> Every stage contains valid data
> Data moves in lock-step
> Bit sequencing and synchronization implicitly enforced
• Async implementation requires explicit control
> Not every stage contains valid data
> Data bits may propagate autonomously
> Must explicitly synchronize pairs of control tokens to
guarantee correct data sequencing.
GASP logic is used here. which is an asynchronous control.
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File list (Check if you may need any files):
LFSR_FIFO_GasP
..............\coding
..............\......\Gasp.v
..............\......\GasP2.v
..............\......\Gasp_8.v
..............\......\Gasp_8_latch.v
..............\......\GasP_dup.v
..............\......\Gasp_Latch.v
..............\......\Gasp_merge.v
..............\......\latch.v
..............\......\lfsr_gasp.v
..............\......\transcript
..............\lfsr_fifo.doc
..............\notes.doc
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