- Category:
- File Formats
- Tags:
-
[WORD]
- File Size:
- 6kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- 邱静
Description: The PLL clock frequency switching process only when the phase-locked loop stable CPU will switch to the new PLL settings. After setting PLLCR need to wait for the PLL to stabilize. The switching time of the PLL is approximately equal to 131 072 input clock cycles.
To Search:
File list (Check if you may need any files):
文档 1.doc
inipll.doc
Download