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- 2013-02-05
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- 吳忠憲
Description: PB5 The ATmega48/88/168 SPI clock output connected to the input end of a 74HC595/74HC165 the shift clock PB4 SPI MISO data input, then 74HC165 data output PB3 SPI MOSI data output, then 74HC595 string The line data input terminal SER PB2 a latch clock input terminal connected 74HC595/74HC165.
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74HC595_74HC165.doc
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