- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 540kb
- Update:
- 2012-12-13
- Downloads:
- 0 Times
- Uploaded by:
- 小白
Description: Electronic bell, development environment based on FPGA Quartus II 6.0. The function is the three buttons to set the hour, minute and second. Usually as courses designed for students to reference to
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clock_for_6.0
.............\SOF.rar
.............\beep_out.vhd
.............\clk_div.vhd
.............\clock_top.asm.rpt
.............\clock_top.done
.............\clock_top.dpf
.............\clock_top.fit.rpt
.............\clock_top.fit.summary
.............\clock_top.flow.rpt
.............\clock_top.map.rpt
.............\clock_top.map.summary
.............\clock_top.pin
.............\clock_top.pof
.............\clock_top.qpf
.............\clock_top.qsf
.............\clock_top.qws
.............\clock_top.sof
.............\clock_top.tan.rpt
.............\clock_top.tan.summary
.............\clock_top.vhd
.............\clock_top_assignment_defaults.qdf
.............\cnt_clock.vhd
.............\db
.............\..\add_sub_a9c.tdf
.............\..\add_sub_b9c.tdf
.............\..\add_sub_c5c.tdf
.............\..\add_sub_c9c.tdf
.............\..\add_sub_d5c.tdf
.............\..\add_sub_d9c.tdf
.............\..\add_sub_e5c.tdf
.............\..\add_sub_e9c.tdf
.............\..\add_sub_f9c.tdf
.............\..\add_sub_lkc.tdf
.............\..\add_sub_mkc.tdf
.............\..\alt_u_div_ake.tdf
.............\..\alt_u_div_cke.tdf
.............\..\alt_u_div_dke.tdf
.............\..\alt_u_div_gke.tdf
.............\..\alt_u_div_kve.tdf
.............\..\alt_u_div_lve.tdf
.............\..\alt_u_div_ove.tdf
.............\..\clock_top.asm.qmsg
.............\..\clock_top.cbx.xml
.............\..\clock_top.cmp.cdb
.............\..\clock_top.cmp.hdb
.............\..\clock_top.cmp.kpt
.............\..\clock_top.cmp.logdb
.............\..\clock_top.cmp.rdb
.............\..\clock_top.cmp.tdb
.............\..\clock_top.cmp0.ddb
.............\..\clock_top.cmp2.ddb
.............\..\clock_top.db_info
.............\..\clock_top.dbp
.............\..\clock_top.eco.cdb
.............\..\clock_top.fit.qmsg
.............\..\clock_top.hier_info
.............\..\clock_top.hif
.............\..\clock_top.map.cdb
.............\..\clock_top.map.hdb
.............\..\clock_top.map.logdb
.............\..\clock_top.map.qmsg
.............\..\clock_top.pre_map.cdb
.............\..\clock_top.pre_map.hdb
.............\..\clock_top.psp
.............\..\clock_top.rtlv.hdb
.............\..\clock_top.rtlv_sg.cdb
.............\..\clock_top.rtlv_sg_swap.cdb
.............\..\clock_top.sgdiff.cdb
.............\..\clock_top.sgdiff.hdb
.............\..\clock_top.sld_design_entry.sci
.............\..\clock_top.sld_design_entry_dsc.sci
.............\..\clock_top.syn_hier_info
.............\..\clock_top.tan.qmsg
.............\..\lpm_divide_25m.tdf
.............\..\lpm_divide_45m.tdf
.............\..\lpm_divide_a6m.tdf
.............\..\lpm_divide_dul.tdf
.............\..\lpm_divide_f1m.tdf
.............\..\lpm_divide_ful.tdf
.............\..\lpm_divide_g1m.tdf
.............\..\lpm_divide_jpl.tdf
.............\..\lpm_divide_lpl.tdf
.............\..\lpm_divide_vcm.tdf
.............\..\sign_div_unsign_4kh.tdf
.............\..\sign_div_unsign_5kh.tdf
.............\..\sign_div_unsign_6kh.tdf
.............\..\sign_div_unsign_7kh.tdf
.............\..\sign_div_unsign_9kh.tdf
.............\..\sign_div_unsign_akh.tdf
.............\..\sign_div_unsign_bkh.tdf
.............\key_ctrl.vhd
.............\led_out.vhd
.............\led_out2.vhd
.............\代码.rar
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