APB_7-SEG_LED_finish_code\APB_testbench\APB\ahb2apb\_primary.dat
.........................\.............\...\.......\_primary.vhd
.........................\.............\...\.......\verilog.asm
.........................\.............\...\......._p8_rec\_primary.dat
.........................\.............\...\..............\_primary.vhd
.........................\.............\...\..............\verilog.asm
.........................\.............\...\muxp2b\_primary.dat
.........................\.............\...\......\_primary.vhd
.........................\.............\...\......\verilog.asm
.........................\.............\...\_info
.........................\.............\work\apb_dummy_slave_rec\_primary.dat
.........................\.............\....\...................\_primary.vhd
.........................\.............\....\...................\verilog.asm
.........................\.............\....\....seg_led\_primary.dat
.........................\.............\....\...........\_primary.vhd
.........................\.............\....\...........\verilog.asm
.........................\.............\....\..........._rec\_primary.dat
.........................\.............\....\...............\_primary.vhd
.........................\.............\....\...............\verilog.asm
.........................\.............\....\bin2seg\_primary.dat
.........................\.............\....\.......\_primary.vhd
.........................\.............\....\.......\verilog.asm
.........................\.............\....\seven_seg\_primary.dat
.........................\.............\....\.........\_primary.vhd
.........................\.............\....\.........\verilog.asm
.........................\.............\....\.im_top\_primary.dat
.........................\.............\....\.......\_primary.vhd
.........................\.............\....\.......\verilog.asm
.........................\.............\....\......._tb\_primary.dat
.........................\.............\....\..........\_primary.vhd
.........................\.............\....\..........\verilog.asm
.........................\.............\....\_info
.........................\.............\APB_7SEG_LED.cr.mti
.........................\.............\APB_7SEG_LED.mpf
.........................\.............\apb_7seg.bmp
.........................\.............\apb_7seg.do
.........................\.............\apb_7seg.wlf
.........................\.............\apb_dummy_slave_rec.v
.........................\.............\apb_seg_led.v
.........................\.............\apb_seg_led_rec.v
.........................\.............\fileconv.pl
.........................\.............\filestim.frd
.........................\.............\filestim.fri
.........................\.............\seven_seg.v
.........................\.............\sim_top.v
.........................\.............\sim_top_tb.v
.........................\.............\transcript
.........................\arm\test\test_Data\Debug\ObjectCode\initmn.o
.........................\...\....\.........\.....\..........\test.o
.........................\...\....\.........\.....\TargetDataWindows.tdt
.........................\...\....\.........\.....\test.axf
.........................\...\....\.........\.....\test.map
.........................\...\....\.........\.....Rel\TargetDataWindows.tdt
.........................\...\....\.........\Release\TargetDataWindows.tdt
.........................\...\....\.........\CWSettingsWindows.stg
.........................\...\....\test.bin
.........................\...\....\test.mcp
.........................\...\config.h
.........................\...\console.h
.........................\...\easySOC.h
.........................\...\initmn.s
.........................\...\test.c
.........................\db\altsyncram_1vi2.tdf
.........................\..\altsyncram_31j2.tdf
.........................\..\altsyncram_9mi1.tdf
.........................\..\altsyncram_a0g2.tdf
.........................\..\altsyncram_a1g2.tdf
.........................\..\alts