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Title: uart_regs Download
 Description: Verilog HDL FPGA-based asynchronous serial communication
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uart_regs
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v
.........\....\myfifo_10_wave0.jpg
.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v
.........\....\myfifo_8_wave0.jpg
.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\a_dpfifo_2r81.tdf
.........\...\..\a_dpfifo_4nl.tdf
.........\...\..\a_dpfifo_lh81.tdf
.........\...\..\a_dpfifo_pp81.tdf
.........\...\..\a_dpfifo_rll.tdf
.........\...\..\a_dpfifo_ui81.tdf
.........\...\..\a_fefifo_66f.tdf
.........\...\..\a_fefifo_qve.tdf
.........\...\..\add_sub_1jh.tdf
.........\...\..\add_sub_dhh.tdf
.........\...\..\add_sub_ehh.tdf
.........\...\..\add_sub_fhh.tdf
.........\...\..\add_sub_ihh.tdf
.........\...\..\add_sub_rih.tdf
.........\...\..\altsyncram_4pl1.tdf
.........\...\..\altsyncram_81m1.tdf
.........\...\..\altsyncram_apb1.tdf
.........\...\..\altsyncram_gml1.tdf
.........\...\..\altsyncram_kul1.tdf
.........\...\..\altsyncram_mmb1.tdf
.........\...\..\cntr_9d7.tdf
.........\...\..\cntr_skb.tdf
.........\...\..\cntr_tcb.tdf
.........\...\..\dpram_2h51.tdf
.........\...\..\dpram_6p51.tdf
.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\dpram_pf51.tdf
.........\...\..\dpram_tn51.tdf
.........\...\..\prev_cmp_uart_regs.asm.qmsg
.........\...\..\prev_cmp_uart_regs.fit.qmsg
.........\...\..\prev_cmp_uart_regs.map.qmsg
.........\...\..\prev_cmp_uart_regs.qmsg
.........\...\..\prev_cmp_uart_regs.tan.qmsg
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_eb81.tdf
.........\...\..\scfifo_ij81.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\scfifo_nc81.tdf
.........\...\..\scfifo_rk81.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs.sld_design_entry.sci
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\greybox_tmp
.........\...\...........\cbx_args.txt
.........\...\incremental_db
.........\...\..............\README
.........\...\..............\compiled_partitions
.........\...\..............\...................\uart_regs.db_info
.........\...\..............\...................\uart_regs.root_partition.map.kpt
.........\...\ledtest.bdf
.........\...\ledtest.v
.........\...\ledtest.v.bak
.........\...\pii0.qip
.........\...\pll.qip
.........\...\rom1.qip
.........\...\sim.cfg
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fit.smsg
.........\...\uart_regs.fit.summary
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.map.summary
.........\...\uart_regs.pin
.........\...\uart_regs.pof
.........\...\uart_regs.qpf
.........\...\uart_regs.qsf
.........\...\uart_regs.qws
.........\...\uart_regs.rbf
.........\...\uart_regs.sim.rpt
.........\...\uart_regs.sof
.........\...\uart_regs.tan.rpt
.........\...\uart_regs.tan.summary
.........\...\uart_regs_assignment_defaults.qdf
.........\sim
.........\...\funcsim
    

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