Description: A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.
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流水线CPU2\cpu\Adder.v
..........\...\ALU.v
..........\...\ALU.v.bak
..........\...\cpu.asm.rpt
..........\...\cpu.done
..........\...\cpu.dpf
..........\...\cpu.fit.rpt
..........\...\cpu.fit.smsg
..........\...\cpu.fit.summary
..........\...\cpu.flow.rpt
..........\...\cpu.map.rpt
..........\...\cpu.map.smsg
..........\...\cpu.map.summary
..........\...\cpu.pin
..........\...\cpu.pof
..........\...\cpu.qpf
..........\...\cpu.qsf
..........\...\cpu.qws
..........\...\cpu.sim.rpt
..........\...\cpu.sof
..........\...\cpu.tan.rpt
..........\...\cpu.tan.summary
..........\...\cpu.v
..........\...\cpu.v.bak
..........\...\cpu.vwf
..........\...\cpu_assignment_defaults.qdf
..........\...\db\altsyncram_5h61.tdf
..........\...\..\altsyncram_7se1.tdf
..........\...\..\altsyncram_i2i1.tdf
..........\...\..\altsyncram_j2i1.tdf
..........\...\..\altsyncram_k2i1.tdf
..........\...\..\altsyncram_p4p1.tdf
..........\...\..\cpu.cbx.xml
..........\...\..\cpu.cmp.rdb
..........\...\..\cpu.cmp_merge.kpt
..........\...\..\cpu.db_info
..........\...\..\cpu.hier_info
..........\...\..\cpu.hif
..........\...\..\cpu.lpc.html
..........\...\..\cpu.lpc.rdb
..........\...\..\cpu.lpc.txt
..........\...\..\cpu.map.kpt
..........\...\..\cpu.map.qmsg
..........\...\..\cpu.map_bb.cdb
..........\...\..\cpu.map_bb.hdb
..........\...\..\cpu.map_bb.logdb
..........\...\..\cpu.pre_map.cdb
..........\...\..\cpu.pre_map.hdb
..........\...\..\cpu.ram0_cpu_1987c.hdl.mif
..........\...\..\cpu.rpp.qmsg
..........\...\..\cpu.rtlv.hdb
..........\...\..\cpu.rtlv_sg.cdb
..........\...\..\cpu.rtlv_sg_swap.cdb
..........\...\..\cpu.sgate.rvd
..........\...\..\cpu.sgate_sm.rvd
..........\...\..\cpu.sgdiff.cdb
..........\...\..\cpu.sgdiff.hdb
..........\...\..\cpu.sim.cvwf
..........\...\..\cpu.sld_design_entry.sci
..........\...\..\cpu.sld_design_entry_dsc.sci
..........\...\..\cpu.smart_action.txt
..........\...\..\cpu.syn_hier_info
..........\...\..\cpu.tis_db_list.ddb
..........\...\..\logic_util_heursitic.dat
..........\...\..\mux_3nc.tdf
..........\...\..\mux_ioc.tdf
..........\...\..\mux_joc.tdf
..........\...\..\mux_t4d.tdf
..........\...\..\prev_cmp_cpu.asm.qmsg
..........\...\..\prev_cmp_cpu.fit.qmsg
..........\...\..\prev_cmp_cpu.map.qmsg
..........\...\..\prev_cmp_cpu.qmsg
..........\...\..\prev_cmp_cpu.sim.qmsg
..........\...\..\prev_cmp_cpu.tan.qmsg
..........\...\..\ram0_cpu_1987c.hdl.mif
..........\...\..\ram1_cpu_1987c.hdl.mif
..........\...\..\ram2_cpu_1987c.hdl.mif
..........\...\..\wed.wsf
..........\...\direct.v
..........\...\direct.v.bak
..........\...\Extend_16to32.v
..........\...\Extend_1to32.v
..........\...\Extend_4to32.v
..........\...\incremental_db\compiled_partitions\cpu.db_info
..........\...\..............\...................\cpu.root_partition.map.cdb
..........\...\..............\...................\cpu.root_partition.map.dpi
..........\...\..............\...................\cpu.root_partition.map.dpi.tmp
..........\...\..............\...................\cpu.root_partition.map.hdb
..........\...\..............\...................\cpu.root_partition.map.kpt
..........\...\..............\README
..........\...\is_immediate.v
..........\...\move.v
..........\...\move.v.bak
..........\...\moveLogic.v
..........\...\moveLogic.v.bak
..........\...\MUX2by1.v
..........\...\MUX2by1_5.v
..........\...\MUX4by1.v
..........\...\MUX5by1.v
..........\...\MUXcontrol.v
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