Description: Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display
To Search:
File list (Check if you may need any files):
ADc.doc
Download