Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: buffer Download
 Description: Receive a serial, parallel send buffer, the data is stored using the dual-port SRAM (read write) to achieve the SRAM size Deep 64 and 32 wide (64-word × 32-bit, see of directory rf2shd4), using the supplied dual-port SRAM. Buffer is connected by a serial input Receiving data, the location of the buffers are full and no longer receive the serial data input and according to the reading request, the order to receive data, will take over Received the full 32-bit data sent, and mark the location of the buffer is empty, can be placed on the new serial input data. Both synchronous and asynchronous serial send method.
 Downloaders recently: [More information of uploader 347624426]
 To Search:
File list (Check if you may need any files):
实验提交\串行接收并行发送FIFO的设计与验证.docx
........\设计源码\SRAM\Memory.v
........\........\....\SRAM.v
........\........\....\Synchronous_Receive.v
........\........\....\test_Memory.v
........\........\....\test_SRAM.v
........\........\....\test_Synchronous_Receive.v
........\........\....2\Asynchronous_Receive.v
........\........\.....\Memory.v
........\........\.....\SRAM2.v
........\........\.....\test_Asynchronous_Receive.v
........\........\.....\test_Memory.v
........\........\.....\test_SRAM2.v
........\........\SRAM
........\........\SRAM2
........\设计源码
实验提交
    

CodeBus www.codebus.net