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Title: Design-and-test-verilog-hdl Download
 Description: Design and test Verilog HDL of CD attached with books
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《设计与验证verilog hdl》配套光盘
.................................\Example-2-1
.................................\...........\HelloVlog.v
.................................\Example-3-1
.................................\...........\FullAdd.v
.................................\...........\transcript
.................................\Example-3-2
.................................\...........\FullAdd.v
.................................\Example-3-3
.................................\...........\CRC10.v
.................................\Example-4-1
.................................\Example-4-10
.................................\............\bibus
.................................\............\.....\bibus.prd
.................................\............\.....\bibus.prj
.................................\............\.....\bibus.v
.................................\............\.....\decode.v
.................................\............\.....\rev_1
.................................\............\.....\.....\bibus.fse
.................................\............\.....\.....\bibus.srd
.................................\............\.....\.....\bibus.srm
.................................\............\.....\.....\bibus.srr
.................................\............\.....\.....\bibus.srs
.................................\............\.....\.....\bibus.sxr
.................................\............\.....\.....\bibus.tcl
.................................\............\.....\.....\bibus.tlg
.................................\............\.....\.....\bibus.vqm
.................................\............\.....\.....\bibus.xrf
.................................\............\.....\.....\bibus_cons.tcl
.................................\............\.....\.....\bibus_rm.tcl
.................................\............\.....\.....\rpt_bibus.areasrr
.................................\............\.....\.....\rpt_bibus_areasrr.htm
.................................\............\.....\.....\syntmp
.................................\............\.....\.....\......\bibus.msg
.................................\............\.....\.....\......\bibus.plg
.................................\............\.....\.....\......\bibus_cons_ui.tcl
.................................\............\.....\.....\verif
.................................\............\.....\.....\.....\bibus.vif
.................................\............\.....\syntmp.msg
.................................\............\complex_bibus
.................................\............\.............\complex_bibus.prd
.................................\............\.............\complex_bibus.prj
.................................\............\.............\complex_bibus.v
.................................\............\.............\complex_bibus2.v
.................................\............\.............\counter.v
.................................\............\.............\decode.v
.................................\............\.............\rev_1
.................................\............\.............\.....\AutoConstraint_complex_bibus.sdc
.................................\............\.............\.....\complex_bibus.fse
.................................\............\.............\.....\complex_bibus.srd
.................................\............\.............\.....\complex_bibus.srm
.................................\............\.............\.....\complex_bibus.srr
.................................\............\.............\.....\complex_bibus.srs
.................................\............\.............\.....\complex_bibus.sxr
.................................\............\.............\.....\complex_bibus.tcl
.................................\............\.............\.....\complex_bibus.tlg
.................................\............\.............\.....\complex_bibus.vqm
.................................\............\.............\.....\complex_bibus.xrf
.................................\............\.............\.....\complex_bibus2.fse
.........................

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