Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: div Download
 Description: I have written a counter divider by adjusting the count period and the count value can be obtained at different frequencies, different duty cycles of the divided clock
 Downloaders recently: [More information of uploader terrylab]
 To Search:
File list (Check if you may need any files): 
div.vhd

CodeBus www.codebus.net