Description: Customize a dual port RAM, DualPortRAM
On the top floor of the RAM engineering instantiation
To realize the project, in Quartus II simulation implement in to make the door level simulation
In ModelSim project to the RTL simulation
To Search:
File list (Check if you may need any files):
Example-b4-1
............\Project
............\.......\db
............\.......\..\altsyncram_9gg1.tdf
............\.......\..\logic_util_heursitic.dat
............\.......\..\prev_cmp_TOP.qmsg
............\.......\..\prev_cmp_TOP.sim.qmsg
............\.......\..\TOP.asm.qmsg
............\.......\..\TOP.asm.rdb
............\.......\..\TOP.cbx.xml
............\.......\..\TOP.cmp.cdb
............\.......\..\TOP.cmp.hdb
............\.......\..\TOP.cmp.kpt
............\.......\..\TOP.cmp.logdb
............\.......\..\TOP.cmp.rdb
............\.......\..\TOP.cmp.tdb
............\.......\..\TOP.cmp0.ddb
............\.......\..\TOP.db_info
............\.......\..\TOP.eco.cdb
............\.......\..\TOP.eds_overflow
............\.......\..\TOP.fit.qmsg
............\.......\..\TOP.hier_info
............\.......\..\TOP.hif
............\.......\..\TOP.lpc.html
............\.......\..\TOP.lpc.rdb
............\.......\..\TOP.lpc.txt
............\.......\..\TOP.map.cdb
............\.......\..\TOP.map.hdb
............\.......\..\TOP.map.logdb
............\.......\..\TOP.map.qmsg
............\.......\..\TOP.pre_map.cdb
............\.......\..\TOP.pre_map.hdb
............\.......\..\TOP.rtlv.hdb
............\.......\..\TOP.rtlv_sg.cdb
............\.......\..\TOP.rtlv_sg_swap.cdb
............\.......\..\TOP.sgdiff.cdb
............\.......\..\TOP.sgdiff.hdb
............\.......\..\TOP.sim.cvwf
............\.......\..\TOP.sim.hdb
............\.......\..\TOP.sim.qmsg
............\.......\..\TOP.sim.rdb
............\.......\..\TOP.sld_design_entry.sci
............\.......\..\TOP.sld_design_entry_dsc.sci
............\.......\..\TOP.smart_action.txt
............\.......\..\TOP.syn_hier_info
............\.......\..\TOP.tan.qmsg
............\.......\..\TOP.tis_db_list.ddb
............\.......\..\wed.wsf
............\.......\DualPortRAM.bsf
............\.......\DualPortRAM.v
............\.......\incremental_db
............\.......\..............\compiled_partitions
............\.......\..............\...................\TOP.root_partition.map.kpt
............\.......\..............\README
............\.......\Simulation
............\.......\..........\altera_mf.v
............\.......\..........\DualPortRAM.v
............\.......\..........\modelsim.ini
............\.......\..........\sim.do
............\.......\..........\TOP.v
............\.......\..........\TOP.vt
............\.......\..........\vsim.wlf
............\.......\..........\wave.do
............\.......\..........\work
............\.......\..........\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
............\.......\..........\....\..........................................\verilog.prw
............\.......\..........\....\..........................................\verilog.psm
............\.......\..........\....\..........................................\_primary.dat
............\.......\..........\....\..........................................\_primary.dbs
............\.......\..........\....\..........................................\_primary.vhd
............\.......\..........\....\@dual@port@r@a@m
............\.......\..........\....\................\verilog.prw
............\.......\..........\....\................\verilog.psm
............\.......\..........\....\................\_primary.dat
............\.......\..........\....\................\_primary.dbs
............\.......\..........\....\................\_primary.vhd
............\.......\..........\....\@m@f_pll_reg
............\.......\..........\....\............\verilog.prw
............\.......\..........\....\............\verilog.psm
............\.......\..........\....\............\_primary.dat
............\.......\..........\....\............\_primary.dbs
............\.......\..........\....\............\_primary.vhd
............\.......\..........\....\@m@f_ram7x20_syn
............\.......\..........\....\................\verilog.prw
............\.......\..........\....\................\verilog.psm
............\.......\..........\....\................\_primary.dat
............\.......\..........\....\...............
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