Title:
A-Fast-CRC-Implementation-on-FPGA
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Description: The CRC error detection is a very
common function on telecommunication applications. The evolution towards increasing data rates requires
more and more sofisticated
implementations. In this paper, we present a method to implement
the CRC function based on a pipeline structure for the
polynomial division. It improves very effectively the
speed performance, allowing data rates from 1 Gbits/s
to 4 Gbits/s on FPGA implementions, according to the
parallelisation level (8 to 32 bits).
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A Fast CRC Implementation on FPGA Using a Pipelined Architecture for the polynomial division.pdf
