Description: Verilog language in the ISE environment, the use of SDRAM control, through functional simulation, which the PLL part and did not join, can join the PLL blocks.
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File list (Check if you may need any files):
sdram
.....\command.v
.....\command.v.bak
.....\control_interface.v
.....\control_interface.v.bak
.....\dcm_test.v
.....\params.v.bak
.....\sdr_data_path.v
.....\sdr_data_path.v.bak
.....\sdr_sdram.v
.....\sdr_sdram.v.bak
.....\tb.v
.....\tb.v.bak
.....\tbcmd.v
.....\tbcmd.v.bak
.....\tbcontrol.v
.....\tbdata.v
.....\tbdata.v.bak
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