Description: upstream channel deinterleaving lte demultiplexing: RTL: ack_addr_gen.vhd ack address generation data_addr_gen.vhd data address generation control unit de_interl_mux_con_top.vhd de_interl_mux_con_ctrl.vhd top de_interl_mux_con_tt.vhd test platform de_mux_ram.vhd ram deinterl_pack.vhd delay variable definition delay.vhd delayb.vhd delay input_buffer.vhd input control information extraction ul_common_pack.vhd ri_addr_gen.vhd ri definition of a variable data source write_ram.vhd deinterleaving deintlv_data.txt deintlv_data_cqi.txt cqi deintlv_data_ack.txt ack information source information sources sources of information deintlv_data_ri.txt ri sim_lib. tcl altera library compile script ue.tcl modelsim
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source\ack_addr_gen.vhd
......\data_addr_gen.vhd
......\deinterl_pack.vhd
......\delay.vhd
......\delayb.vhd
......\de_interl_mux_con_ctrl.vhd
......\de_interl_mux_con_top.vhd
......\de_interl_mux_con_tt.vhd
......\de_mux_ram.vhd
......\de_mux_ram_wave0.jpg
......\de_mux_ram_wave1.jpg
......\input_buffer.vhd
......\ri_addr_gen.vhd
......\ul_common_pack.vhd
......\write_ram.vhd
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