Title:
Nios_Example_07_SD_35TFT
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Description: This is a nios engineering, control TFT LCD screen program. The FPGA platform Verilog HDL language preparation with the nuclear program has a soft, MCU written in C language. Through this a complete project, you will understand some of the SOPC methods of realization.
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RedCore_EP2C8Q_V1_Nios_Example_07_SD_35TFT\LCD_CS.v
..........................................\LCD_DATA.v
..........................................\LCD_RD.v
..........................................\LCD_RS.v
..........................................\LCD_RST.v
..........................................\LCD_WR.v
..........................................\LED.v
..........................................\PLL.v
..........................................\RedCore_EP2C8Q_V1_Nios_Example.asm.rpt
..........................................\RedCore_EP2C8Q_V1_Nios_Example.bsf
..........................................\RedCore_EP2C8Q_V1_Nios_Example.done
..........................................\RedCore_EP2C8Q_V1_Nios_Example.dpf
..........................................\RedCore_EP2C8Q_V1_Nios_Example.fit.rpt
..........................................\RedCore_EP2C8Q_V1_Nios_Example.fit.smsg
..........................................\RedCore_EP2C8Q_V1_Nios_Example.fit.summary
..........................................\RedCore_EP2C8Q_V1_Nios_Example.flow.rpt
..........................................\RedCore_EP2C8Q_V1_Nios_Example.html
..........................................\RedCore_EP2C8Q_V1_Nios_Example.jdi
..........................................\RedCore_EP2C8Q_V1_Nios_Example.map.rpt
..........................................\RedCore_EP2C8Q_V1_Nios_Example.map.smsg
..........................................\RedCore_EP2C8Q_V1_Nios_Example.map.summary
..........................................\RedCore_EP2C8Q_V1_Nios_Example.pin
..........................................\RedCore_EP2C8Q_V1_Nios_Example.pof
..........................................\RedCore_EP2C8Q_V1_Nios_Example.ptf
..........................................\RedCore_EP2C8Q_V1_Nios_Example.ptf.8.0
..........................................\RedCore_EP2C8Q_V1_Nios_Example.ptf.bak
..........................................\RedCore_EP2C8Q_V1_Nios_Example.ptf.pre_generation_ptf
..........................................\RedCore_EP2C8Q_V1_Nios_Example.qip
..........................................\RedCore_EP2C8Q_V1_Nios_Example.qpf
..........................................\RedCore_EP2C8Q_V1_Nios_Example.qsf
..........................................\RedCore_EP2C8Q_V1_Nios_Example.sof
..........................................\RedCore_EP2C8Q_V1_Nios_Example.sopc
..........................................\RedCore_EP2C8Q_V1_Nios_Example.sopcinfo
..........................................\RedCore_EP2C8Q_V1_Nios_Example.tan.rpt
..........................................\RedCore_EP2C8Q_V1_Nios_Example.tan.summary
..........................................\RedCore_EP2C8Q_V1_Nios_Example.v
..........................................\RedCore_EP2C8Q_V1_Nios_Example.v.bak
..........................................\RedCore_EP2C8Q_V1_Nios_Example_generation_script
..........................................\RedCore_EP2C8Q_V1_Nios_Example_inst.v
..........................................\RedCore_EP2C8Q_V1_Nios_Example_log.txt
..........................................\SD_CLK.v
..........................................\SD_CS.v
..........................................\SD_DI.v
..........................................\SD_DO.v
..........................................\cpu_0.ocp
..........................................\cpu_0.sdc
..........................................\cpu_0.v
..........................................\cpu_0_bht_ram.mif
..........................................\cpu_0_dc_tag_ram.mif
..........................................\cpu_0_ic_tag_ram.mif
..........................................\cpu_0_jtag_debug_module_sysclk.v
..........................................\cpu_0_jtag_debug_module_tck.v
..........................................\cpu_0_jtag_debug_module_wrapper.v
..........................................\cpu_0_mult_cell.v
..........................................\cpu_0_oci_test_bench.v
..........................................\cpu_0_ociram_default_contents.mif
..........................................\cpu_0_rf_ram_a.mif
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