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Title: divider_60 Download
 Description: Verilog language with a digital clock, support platform is alter the company cyloneII.
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divider_60
..........\db
..........\..\divider_60.db_info
..........\..\divider_60.eco.cdb
..........\..\divider_60.sld_design_entry.sci
..........\divider_24.bsf
..........\divider_24.v
..........\divider_60.bsf
..........\divider_60.qpf
..........\divider_60.qsf
..........\divider_60.qws
..........\divider_60.v
..........\electronic_clock.bdf
..........\f_divider.v
..........\led_display.bsf
..........\led_display.v
    

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