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Title: uart Download
 Description: FPGA based multi-port instruction Motor Closed Loop System
 Downloaders recently: [More information of uploader 740720618]
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  • [lcd1602] - Written lcd1602 with verilog
  • [MAC] - FPGA-based mac Verilog source code sub-l
  • [EP2C5] - Development board based on more routine
  • [uart] - A simple serial port controller, to achi
File list (Check if you may need any files):
uart测试版\.sopc_builder\filters.xml
..........\db\add_sub_0fc.tdf
..........\..\add_sub_1fc.tdf
..........\..\add_sub_2fc.tdf
..........\..\add_sub_3dc.tdf
..........\..\add_sub_4dc.tdf
..........\..\add_sub_5dc.tdf
..........\..\add_sub_6dc.tdf
..........\..\add_sub_7dc.tdf
..........\..\add_sub_8dc.tdf
..........\..\add_sub_9dc.tdf
..........\..\add_sub_adc.tdf
..........\..\add_sub_bdc.tdf
..........\..\add_sub_jec.tdf
..........\..\add_sub_kec.tdf
..........\..\add_sub_lec.tdf
..........\..\add_sub_mec.tdf
..........\..\add_sub_nec.tdf
..........\..\add_sub_oec.tdf
..........\..\add_sub_pec.tdf
..........\..\add_sub_qec.tdf
..........\..\add_sub_rec.tdf
..........\..\add_sub_sec.tdf
..........\..\add_sub_tec.tdf
..........\..\add_sub_uec.tdf
..........\..\add_sub_vec.tdf
..........\..\alt_u_div_0re.tdf
..........\..\alt_u_div_0ue.tdf
..........\..\alt_u_div_2ue.tdf
..........\..\alt_u_div_3ue.tdf
..........\..\alt_u_div_4re.tdf
..........\..\alt_u_div_4ue.tdf
..........\..\alt_u_div_5re.tdf
..........\..\alt_u_div_5ue.tdf
..........\..\alt_u_div_6re.tdf
..........\..\alt_u_div_6ue.tdf
..........\..\alt_u_div_8re.tdf
..........\..\alt_u_div_8ue.tdf
..........\..\alt_u_div_are.tdf
..........\..\alt_u_div_aue.tdf
..........\..\alt_u_div_cue.tdf
..........\..\alt_u_div_ere.tdf
..........\..\alt_u_div_gue.tdf
..........\..\alt_u_div_ote.tdf
..........\..\alt_u_div_qte.tdf
..........\..\alt_u_div_rte.tdf
..........\..\alt_u_div_ste.tdf
..........\..\alt_u_div_uqe.tdf
..........\..\lpm_divide_07m.tdf
..........\..\lpm_divide_17m.tdf
..........\..\lpm_divide_1vl.tdf
..........\..\lpm_divide_27m.tdf
..........\..\lpm_divide_37m.tdf
..........\..\lpm_divide_3vl.tdf
..........\..\lpm_divide_88m.tdf
..........\..\lpm_divide_98m.tdf
..........\..\lpm_divide_a8m.tdf
..........\..\lpm_divide_b8m.tdf
..........\..\lpm_divide_c8m.tdf
..........\..\lpm_divide_d8m.tdf
..........\..\lpm_divide_e8m.tdf
..........\..\lpm_divide_f8m.tdf
..........\..\lpm_divide_g8m.tdf
..........\..\lpm_divide_h8m.tdf
..........\..\lpm_divide_i8m.tdf
..........\..\lpm_divide_j8m.tdf
..........\..\lpm_divide_k8m.tdf
..........\..\lpm_divide_l8m.tdf
..........\..\lpm_divide_r6m.tdf
..........\..\lpm_divide_s6m.tdf
..........\..\lpm_divide_u6m.tdf
..........\..\lpm_divide_uul.tdf
..........\..\lpm_divide_v6m.tdf
..........\..\lpm_divide_vul.tdf
..........\..\prev_cmp_uart.asm.qmsg
..........\..\prev_cmp_uart.eda.qmsg
..........\..\prev_cmp_uart.fit.qmsg
..........\..\prev_cmp_uart.map.qmsg
..........\..\prev_cmp_uart.qmsg
..........\..\prev_cmp_uart.tan.qmsg
..........\..\sign_div_unsign_4nh.tdf
..........\..\sign_div_unsign_5nh.tdf
..........\..\sign_div_unsign_6nh.tdf
..........\..\sign_div_unsign_7nh.tdf
..........\..\sign_div_unsign_8nh.tdf
..........\..\sign_div_unsign_9nh.tdf
..........\..\sign_div_unsign_anh.tdf
..........\..\sign_div_unsign_bnh.tdf
..........\..\sign_div_unsign_cnh.tdf
..........\..\sign_div_unsign_dnh.tdf
..........\..\sign_div_unsign_enh.tdf
..........\..\sign_div_unsign_fnh.tdf
..........\..\sign_div_unsign_gnh.tdf
..........\..\sign_div_unsign_hnh.tdf
..........\..\sign_div_unsign_nlh.tdf
..........\..\sign_div_unsign_olh.tdf
..........\..\sign_div_unsign_qlh.tdf
..........\..\sign_div_unsign_rlh.tdf
..........\..\sign_div_unsign_slh.tdf
..........\..\sign_div_unsign_tlh.tdf
    

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