spi SPI bus interface in verilog source code, incl

Title: spi

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
284kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
阿虎

Description: SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.

Downloaders recently: [More information of uploader 阿虎]

To Search: spi master verilog r

[spidmadriver] - the driver linux2.6.17 in which the test
[spi] - VHDL SPI interface, the application of A
[SPI_Code(Verilog)] - SPI bus under the Verilog hardware descr
[spi_op_core] - Verilog programming SPI protocol, includ
[components] - quartus several IP core (PWM, RAM, I2C)
[SPI] - the design of SPI controlor ,including v
[SPI_controller] - SPI serial flash ROM in verilog source c
[SPI] - spi IP based on fpga
[SPI-in-Verilog-implementation] - SPI in Verilog implementation (a very fu
[SPI_slave-fpga_arm] - communicateion FPGA and ARM using SPI

File list (Check if you may need any files):

spi\code\SPI_Master.v
...\modelsim\SPI_Master.cr.mti
...\........\SPI_Master.mpf
...\........\SPI_Master.v
...\........\SPI_Master_test.v
...\........\SPI_Master_test.v.bak
...\........\transcript
...\........\vsim.wlf
...\........\wave.bmp
...\........\wave.do
...\........\.ork\@s@p@i_@master\verilog.psm
...\........\....\..............\_primary.dat
...\........\....\..............\_primary.vhd
...\........\....\.......master_test\transcript
...\........\....\..................\verilog.psm
...\........\....\..................\_primary.dat
...\........\....\..................\_primary.vhd
...\........\....\_info
...\quartus\cmp_state.ini
...\.......\db\prev_cmp_SPI_Master.asm.qmsg
...\.......\..\prev_cmp_SPI_Master.fit.qmsg
...\.......\..\prev_cmp_SPI_Master.map.qmsg
...\.......\..\prev_cmp_SPI_Master.tan.qmsg
...\.......\..\SPI_Master.asm.qmsg
...\.......\..\SPI_Master.cbx.xml
...\.......\..\SPI_Master.cmp.cdb
...\.......\..\SPI_Master.cmp.ddb
...\.......\..\SPI_Master.cmp.hdb
...\.......\..\SPI_Master.cmp.logdb
...\.......\..\SPI_Master.cmp.rdb
...\.......\..\SPI_Master.cmp.tdb
...\.......\..\SPI_Master.csf.qmsg
...\.......\..\SPI_Master.dbp
...\.......\..\SPI_Master.db_info
...\.......\..\SPI_Master.fit.qmsg
...\.......\..\SPI_Master.hier_info
...\.......\..\SPI_Master.hif
...\.......\..\SPI_Master.icc
...\.......\..\SPI_Master.map.cdb
...\.......\..\SPI_Master.map.hdb
...\.......\..\SPI_Master.map.logdb
...\.......\..\SPI_Master.map.qmsg
...\.......\..\SPI_Master.pre_map.hdb
...\.......\..\SPI_Master.project.hdb
...\.......\..\SPI_Master.psp
...\.......\..\SPI_Master.pss
...\.......\..\SPI_Master.rtlv.hdb
...\.......\..\SPI_Master.rtlv_sg.cdb
...\.......\..\SPI_Master.rtlv_sg_swap.cdb
...\.......\..\SPI_Master.sgdiff.cdb
...\.......\..\SPI_Master.sgdiff.hdb
...\.......\..\SPI_Master.SPI_Master.sld_design_entry.sci
...\.......\..\SPI_Master.syn_hier_info
...\.......\..\SPI_Master.tan.qmsg
...\.......\..\SPI_Master_cmp.qrpt
...\.......\..\SPI_Master_hier_info
...\.......\..\SPI_Master_syn_hier_info
...\.......\SPI_Master.asm.rpt
...\.......\SPI_Master.bsf
...\.......\SPI_Master.done
...\.......\SPI_Master.dpf
...\.......\SPI_Master.fit.eqn
...\.......\SPI_Master.fit.rpt
...\.......\SPI_Master.fit.smsg
...\.......\SPI_Master.fit.summary
...\.......\SPI_Master.flow.rpt
...\.......\SPI_Master.map.eqn
...\.......\SPI_Master.map.rpt
...\.......\SPI_Master.map.smsg
...\.......\SPI_Master.map.summary
...\.......\SPI_Master.pin
...\.......\SPI_Master.pof
...\.......\SPI_Master.qpf
...\.......\SPI_Master.qsf
...\.......\SPI_Master.qws
...\.......\SPI_Master.tan.rpt
...\.......\SPI_Master.tan.summary
...\.......\SPI_Master.v
...\.......\SPI_Master_assignment_defaults.qdf
...\.......\SPI_master_test.bsf
...\.......\test.bdf
...\testbench\SPI_Master_test.v
...\.........\transcript
...\modelsim\work\@s@p@i_@master
...\........\....\@s@p@i_master_test
...\........\work
...\quartus\db
...\code
...\modelsim
...\quartus
...\testbench
spi

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