Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: traffic-control Download
 Description: Only four traffic lights to design a traffic signal controller: from a main road and- bar branch roads merged into the crossroads, the entrance of each set of red, green, yellow, turn left to allow four lights, red light is closed to traffic, the green light to allow passage, the yellow light is to have time to moving vehicles parked outside the line of the cut line, allowing the vehicle to the left turn left turn lights. The order of signal conversion: the main branch roads alternately allow passage, each trunk release 40s, 5s bright red light to moving vehicles have time to stop the entry lane, the left release of 15s, 5s grams of red light branch trunk release 30s, 5s bright yellow light, turn left release 15s, 5s red light ... .... The countdown timer circuit.
 Downloaders recently: [More information of uploader jiaoanbolinux]
 To Search:
File list (Check if you may need any files):
traffic control.docx
    

CodeBus www.codebus.net