SDRAM控制器Verilog HDL源码\readme_sdr_sdram.txt
..........................\sdr_sdram.pdf
..........................\.imulation\sdr_sdram_tb.v
..........................\.ource\altclklock.v
..........................\......\Command.v
..........................\......\compile_all.v
..........................\......\control_interface.v
..........................\......\Params.v
..........................\......\PLL1.v
..........................\......\sdr_data_path.v
..........................\......\sdr_sdram.v
..........................\使用说明请参看右侧注释====〉〉.txt
..........................\doc
..........................\simulation
..........................\source
SDRAM控制器Verilog HDL源码