Description: PCI Bus (Slave) interface to FPGA implementation of the code, all source code files for the Verilog language, but also test the code, included the design and practical documentation.
File list (Check if you may need any files):
PCI_Altera\base_addr_chk.v
..........\config_mux.v
..........\glue.v
..........\pargen.v
..........\pci_top.v
..........\pci总线接口Verilog设计使用手册.pdf
..........\retry_count.v
..........\state_machine.v
..........\tstbench\bkend_daemon.v
..........\........\pci_clk_reset.v
..........\........\pci_stim.v
..........\........\pci_tb.v
..........\........\tasks.v
..........\waveperl.log
..........\tstbench
PCI_Altera
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