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Title: 8bitcpunew Download
 Description: 8-bit cpu, fpga programming instructions to achieve 29 development board verified by
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File list (Check if you may need any files):
8bitcpunew
..........\8bitcpu1
..........\........\.sopc_builder
..........\........\.............\filters.xml
..........\........\8bitcpu.asm.rpt
..........\........\8bitcpu.cdf
..........\........\8bitcpu.cr.mti
..........\........\8bitcpu.done
..........\........\8bitcpu.dpf
..........\........\8bitcpu.drc.rpt
..........\........\8bitcpu.eda.rpt
..........\........\8bitcpu.fit.rpt
..........\........\8bitcpu.fit.smsg
..........\........\8bitcpu.fit.summary
..........\........\8bitcpu.flow.rpt
..........\........\8bitcpu.map.rpt
..........\........\8bitcpu.map.smsg
..........\........\8bitcpu.map.summary
..........\........\8bitcpu.mpf
..........\........\8bitcpu.pin
..........\........\8bitcpu.pof
..........\........\8bitcpu.qpf
..........\........\8bitcpu.qsf
..........\........\8bitcpu.qws
..........\........\8bitcpu.sim.rpt
..........\........\8bitcpu.sof
..........\........\8bitcpu.tan.rpt
..........\........\8bitcpu.tan.summary
..........\........\8bitcpu.vwf
..........\........\8bitcpu_assignment_defaults.qdf
..........\........\ALU.v
..........\........\ALU.v.bak
..........\........\Chain1.cdf
..........\........\clk
..........\........\...\clk.asm.rpt
..........\........\...\clk.done
..........\........\...\clk.fit.rpt
..........\........\...\clk.fit.summary
..........\........\...\clk.flow.rpt
..........\........\...\clk.map.rpt
..........\........\...\clk.map.summary
..........\........\...\clk.pin
..........\........\...\clk.pof
..........\........\...\clk.qpf
..........\........\...\clk.qsf
..........\........\...\clk.qws
..........\........\...\clk.sim.rpt
..........\........\...\clk.sof
..........\........\...\clk.tan.rpt
..........\........\...\clk.tan.summary
..........\........\...\clk.vwf
..........\........\...\clock.v
..........\........\...\clock.v.bak
..........\........\...\db
..........\........\...\..\clk.asm.qmsg
..........\........\...\..\clk.cbx.xml
..........\........\...\..\clk.cmp.cdb
..........\........\...\..\clk.cmp.hdb
..........\........\...\..\clk.cmp.logdb
..........\........\...\..\clk.cmp.rdb
..........\........\...\..\clk.cmp.tdb
..........\........\...\..\clk.cmp0.ddb
..........\........\...\..\clk.db_info
..........\........\...\..\clk.eco.cdb
..........\........\...\..\clk.eds_overflow
..........\........\...\..\clk.fit.qmsg
..........\........\...\..\clk.hier_info
..........\........\...\..\clk.hif
..........\........\...\..\clk.lpc.html
..........\........\...\..\clk.lpc.rdb
..........\........\...\..\clk.lpc.txt
..........\........\...\..\clk.map.cdb
..........\........\...\..\clk.map.hdb
..........\........\...\..\clk.map.logdb
..........\........\...\..\clk.map.qmsg
..........\........\...\..\clk.pre_map.cdb
..........\........\...\..\clk.pre_map.hdb
..........\........\...\..\clk.rtlv.hdb
..........\........\...\..\clk.rtlv_sg.cdb
..........\........\...\..\clk.rtlv_sg_swap.cdb
..........\........\...\..\clk.sgdiff.cdb
..........\........\...\..\clk.sgdiff.hdb
..........\........\...\..\clk.sim.cvwf
..........\........\...\..\clk.sim.hdb
..........\........\...\..\clk.sim.qmsg
..........\........\...\..\clk.sim.rdb
..........\........\...\..\clk.sld_design_entry.sci
..........\........\...\..\clk.sld_design_entry_dsc.sci
..........\........\...\..\clk.syn_hier_info
..........\........\...\..\clk.tan.qmsg
..........\........\...\..\clk.tis_db_list.ddb
..........\........\...\..\clk.tmw_info
..........\........\...\..\prev_cmp_clk.asm.qmsg
..........\........\...\..\prev_cmp_clk.fit.qmsg
..........\........\...\..\prev_cmp_clk.map.qmsg
..........\........\...\..\prev_cmp_clk.qmsg
..........\........\...\..\prev_cmp_clk.sim.qmsg
..........\........\...\..\prev_cmp_clk.tan.qmsg
..........\........\...\..\wed.wsf
..........\........\...\incremental_db
    

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