Title:
get-start-with-modulesim
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Description: Altera FPGA-based embedded chip company with modulesim simulation steps, and detailed examples, how to use the church modulesim testbench simulation and preparation procedures.
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get start with modulesim.txt
simulation
..........\modelsim
..........\........\de1_t1.sft
..........\........\de1_t1.vo
..........\........\de1_t1.vt
..........\........\de1_t1.vt.bak
..........\........\de1_t1_modelsim.xrf
..........\........\de1_t1_run_msim_rtl_verilog.do
..........\........\de1_t1_run_msim_rtl_verilog.do.bak
..........\........\de1_t1_run_msim_rtl_verilog.do.bak1
..........\........\de1_t1_run_msim_rtl_verilog.do.bak2
..........\........\de1_t1_run_msim_rtl_verilog.do.bak3
..........\........\de1_t1_run_msim_rtl_verilog.do.bak4
..........\........\de1_t1_run_msim_rtl_verilog.do.bak5
..........\........\de1_t1_run_msim_rtl_verilog.do.bak6
..........\........\de1_t1_run_msim_rtl_verilog.do.bak7
..........\........\de1_t1_run_msim_rtl_verilog.do.bak8
..........\........\de1_t1_v.sdo
..........\........\modelsim.ini
..........\........\msim_transcript
..........\........\rtl_work
..........\........\........\@crt_clk_bps
..........\........\........\............\verilog.psm
..........\........\........\............\_primary.dat
..........\........\........\............\_primary.dbs
..........\........\........\............\_primary.vhd
..........\........\........\@s@e@g7_@l@u@t
..........\........\........\..............\verilog.psm
..........\........\........\..............\_primary.dat
..........\........\........\..............\_primary.dbs
..........\........\........\..............\_primary.vhd
..........\........\........\@s@e@g7_@l@u@t_4
..........\........\........\................\verilog.psm
..........\........\........\................\_primary.dat
..........\........\........\................\_primary.dbs
..........\........\........\................\_primary.vhd
..........\........\........\@s@t@a@r@t_@t@x
..........\........\........\...............\verilog.psm
..........\........\........\...............\_primary.dat
..........\........\........\...............\_primary.dbs
..........\........\........\...............\_primary.vhd
..........\........\........\@uart_tx
..........\........\........\........\verilog.psm
..........\........\........\........\_primary.dat
..........\........\........\........\_primary.dbs
..........\........\........\........\_primary.vhd
..........\........\........\@v@g@a_controller
..........\........\........\.................\verilog.psm
..........\........\........\.................\_primary.dat
..........\........\........\.................\_primary.dbs
..........\........\........\.................\_primary.vhd
..........\........\........\de1_t1
..........\........\........\......\verilog.psm
..........\........\........\......\_primary.dat
..........\........\........\......\_primary.dbs
..........\........\........\......\_primary.vhd
..........\........\........\de1_t1_vlg_tst
..........\........\........\..............\verilog.psm
..........\........\........\..............\_primary.dat
..........\........\........\..............\_primary.dbs
..........\........\........\..............\_primary.vhd
..........\........\........\pll_control
..........\........\........\...........\verilog.psm
..........\........\........\...........\_primary.dat
..........\........\........\...........\_primary.dbs
..........\........\........\...........\_primary.vhd
..........\........\........\_info
..........\........\........\_temp
..........\........\........\_vmake
..........\........\vsim.wlf
