Description: * FullAdder implementation in VHDL with respectives signals:
a, b : in std_logic_vector (7 downto 0)
soma : out std_logic_vector (7 downto 0)
ci : in std_logic
co : out std_logic
overflow : out std_logic
negativo : out std_logic
zero : out std_logic
* TestBench implementation for FullAdder.
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File list (Check if you may need any files):
TESTE_FA.vhdl
FULLADDER.vhdl
Somador_8bits.vhdl
TESTE.vhdl
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