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Title: DS-Verilog Download
 Description: ad
 Downloaders recently: [More information of uploader 309933041]
 To Search: ad verilog
  • [AD] - FPGA control module of the AD7321 is per
  • [C6748evm-bsl] - TI company-OMAPL138EVM board C6748BSL (B
File list (Check if you may need any files):
DS-Verilog\DS\DS.prj
..........\..\说明.txt
..........\..\DS.prj.convert.7.3.bak
..........\..\component
..........\..\hdl\Adc.v
..........\..\...\SPI.v
..........\..\...\Distace.v
..........\..\hdl
..........\..\designer\impl1\Adc.tcl
..........\..\........\.....\Adc.ide_des
..........\..\........\.....\Distace.lok
..........\..\........\.....\Distace.adb
..........\..\........\.....\ada02724-1.tmp
..........\..\........\.....\Distace.adl
..........\..\........\.....\Adc.adb
..........\..\........\.....\designer.log
..........\..\........\.....\Adc.adl
..........\..\........\.....\Distace.tcl
..........\..\........\.....\Distace.ide_des
..........\..\........\.....\Distace-am.sdf
..........\..\........\.....\Distace.bit
..........\..\........\.....\Distace_ba.sdf
..........\..\........\.....\Distace_ba.v
..........\..\........\.....\Distace.vnm
..........\..\........\.....\flashpro.log
..........\..\........\.....\Distace.stp
..........\..\........\.....\......._fp\Distace.log
..........\..\........\.....\..........\Distace.pro
..........\..\........\.....\..........\projectData\Distace.stp
..........\..\........\.....\..........\projectData
..........\..\........\.....\Distace_fp
..........\..\........\.....\........dtf\master.gcf
..........\..\........\.....\...........\master-des.gcf
..........\..\........\.....\...........\import.log
..........\..\........\.....\...........\masks
..........\..\........\.....\...........\floorplan.gcf
..........\..\........\.....\...........\floorplan.gcf.old
..........\..\........\.....\...........\place.log
..........\..\........\.....\...........\last_placement.gcf
..........\..\........\.....\...........\mem_plmt.gcf
..........\..\........\.....\...........\masks.final
..........\..\........\.....\...........\route.log
..........\..\........\.....\...........\time.log
..........\..\........\.....\...........\bitgen.log
..........\..\........\.....\...........\initial_placement.gcf
..........\..\........\.....\...........\floorplan-des.gcf
..........\..\........\.....\Distace.dtf
..........\..\........\.....\Adc.dtf\master.gcf
..........\..\........\.....\.......\master-des.gcf
..........\..\........\.....\.......\import.log
..........\..\........\.....\.......\masks
..........\..\........\.....\.......\inverted_ports
..........\..\........\.....\.......\floorplan.gcf
..........\..\........\.....\Adc.dtf
..........\..\........\.....\simulation
..........\..\........\impl1
..........\..\designer
..........\..\stimulus
..........\..\phy_synthesis
..........\..\synthesis\Distace.srr
..........\..\.........\stdout.log
..........\..\.........\Distace.tlg
..........\..\.........\Distace.srs
..........\..\.........\Distace_syn.prj
..........\..\.........\Distace_syn.prd
..........\..\.........\Distace.srd
..........\..\.........\Distace.srm
..........\..\.........\Adc.srr
..........\..\.........\Adc.tlg
..........\..\.........\Distace.map
..........\..\.........\Distace.edn
..........\..\.........\Distace.sdf
..........\..\.........\Distace_sdc.sdc
..........\..\.........\Distace.areasrr
..........\..\.........\Adc_syn.prj
..........\..\.........\traplog.tlg
..........\..\.........\.recordref
..........\..\.........\Adc.srd
..........\..\.........\Adc.srm
..........\..\.........\Adc.map
..........\..\.........\Adc.edn
..........\..\.........\Adc.sdf
..........\..\.........\Adc_sdc.sdc
..........\..\.........\Adc.areasrr
..........\..\.........\Adc_syn.prd
..........\..\.........\Adc.srs
..........\..\.........\syntmp\Adc.plg
..........\..\.........\......\Adc.msg
..........\..\.........\......\Distace.msg
..........\..\.........\......\Distace.plg
..........\..\.........\syntmp
..........\..\synthesis
..........\..\.imulation\meminit.dat
..........\..\..........\modelsim.ini.sav
..........\..\..........\modelsim.ini
..........\..\simulation
..........\..\coreconsole
..........\..\smartgen\smartgen.aws
..........\..\smartgen
..........\..\viewdraw\viewdraw.ini
    

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