uart 源码 (VHDL)\address_decode_rtl.vhd
................\clock_divider.v
................\control_operation_fsm.vhd
................\cpu_interface_rtl.vhd
................\serial_interface_rtl.vhd
................\status_registers_rtl.vhd
................\tester.v
................\uart_tb.v
................\uart_top_rtl.vhd
................\xmit_rcv_control_fsm.vhd
uart 源码 (VHDL)