Description: This is achieved mainly two kinds of RGB and YUV color space conversion, which uses the main idea is, verilog language how floating point multiplication operations, lines of thought.
To Search:
- [at91_spi] - High speed frame transmit/receive using
- [Verilog] - Verilog description of three-stage state
- [fpga_frame] - Test code, using fpga send a raw video f
- [ad7366] - AD7366 control programme
- [Convolution-code-] - Convolution code
- [dac] - DA-chip SPI protocol output control does
File list (Check if you may need any files):
rgb2yuv1\.lso
........\all.do
........\device_usage_statistics.html
........\fuse.log
........\isim.cmd
........\isim.hdlsourcefiles
........\isim.log
........\isimwavedata.xwv
........\rgb2yuv1.bgn
........\rgb2yuv1.bit
........\rgb2yuv1.bld
........\rgb2yuv1.cmd_log
........\rgb2yuv1.drc
........\rgb2yuv1.ise
........\rgb2yuv1.lfp
........\rgb2yuv1.lso
........\rgb2yuv1.ncd
........\rgb2yuv1.ngc
........\rgb2yuv1.ngd
........\rgb2yuv1.ngr
........\rgb2yuv1.ntrc_log
........\rgb2yuv1.pad
........\rgb2yuv1.par
........\rgb2yuv1.pcf
........\rgb2yuv1.prj
........\rgb2yuv1.ptwx
........\rgb2yuv1.restore
........\rgb2yuv1.stx
........\rgb2yuv1.syr
........\rgb2yuv1.twr
........\rgb2yuv1.twx
........\rgb2yuv1.ucf
........\rgb2yuv1.udo
........\rgb2yuv1.unroutes
........\rgb2yuv1.ut
........\rgb2yuv1.v
........\rgb2yuv1.xpi
........\rgb2yuv1.xst
........\rgb2yuv1_beh.prj
........\rgb2yuv1_guide.ncd
........\rgb2yuv1_isim_beh.exe
........\rgb2yuv1_isim_beh.wfs
........\rgb2yuv1_map.map
........\rgb2yuv1_map.mrp
........\rgb2yuv1_map.ncd
........\rgb2yuv1_map.ngm
........\rgb2yuv1_map.xrpt
........\rgb2yuv1_ngdbuild.xrpt
........\rgb2yuv1_pad.csv
........\rgb2yuv1_pad.txt
........\rgb2yuv1_par.xrpt
........\rgb2yuv1_prev_built.ngd
........\rgb2yuv1_stx.prj
........\rgb2yuv1_summary.html
........\rgb2yuv1_summary.xml
........\rgb2yuv1_tbw.ant
........\rgb2yuv1_tbw.jhd
........\rgb2yuv1_tbw.tbw
........\rgb2yuv1_tbw.tfw
........\rgb2yuv1_tbw.xwv
........\rgb2yuv1_tbw.xwv_bak
........\rgb2yuv1_tbw_beh.prj
........\rgb2yuv1_tbw_bencher.prj
........\rgb2yuv1_tbw_isim_beh.exe
........\rgb2yuv1_tbw_isim_beh.wfs
........\rgb2yuv1_usage.xml
........\rgb2yuv1_wave.fdo
........\rgb2yuv1_xst.xrpt
........\rgb2yuv_tf.fdo
........\rgb2yuv_tf.udo
........\rgb2yuv_tf.v
........\rgb2yuv_tf_wave.fdo
........\tmpRTVStore.xwv
........\transcript
........\vsim.wlf
........\xilinxsim.ini
........\_xmsgs\bitgen.xmsgs
........\......\map.xmsgs
........\......\ngdbuild.xmsgs
........\......\par.xmsgs
........\......\trce.xmsgs
........\......\xst.xmsgs
........\.ngo\netlist.lst
........\xst\work\hdllib.ref
........\...\....\vlg06\rgb2yuv1.bin
........\...\dump.xst\rgb2yuv1.prj\ntrc.scr
........\work\_info
........\....\rgb2yuv_tf\verilog.asm
........\....\..........\_primary.dat
........\....\..........\_primary.vhd
........\....\.......1\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\glbl\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\rgb2yuv1_xdb\cst.xbcd
........\............\tmp\ise.lock
........\............\...\...\version
........\............\...\...\__REGISTRY__\_ProjRepoInternal_\regkeys
Download