Description: This is mainly the double in xilinx FPGA DCM connection problem which little information online, their own studies and simulation can be achieved after the normal work of the two dcm achieve clock frequency and the inverse
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File list (Check if you may need any files):
double_dcm\coregen.cgc
..........\coregen.cgp
..........\dcm1.v
..........\dcm1_arwz.ucf
..........\dcm1_summary.html
..........\dcm2.v
..........\dcm2_arwz.ucf
..........\double_dcm.gise
..........\double_dcm.xise
..........\ipcore_dir\dcm1.cgc
..........\..........\dcm1.cgp
..........\..........\dcm1.v
..........\..........\dcm1.xaw
..........\..........\dcm1_arwz.ucf
..........\..........\dcm1_flist.txt
..........\..........\dcm1_readme.txt
..........\..........\dcm1_xmdf.tcl
..........\..........\dcm2.cgc
..........\..........\dcm2.cgp
..........\..........\dcm2.v
..........\..........\dcm2.xaw
..........\..........\dcm2_arwz.ucf
..........\..........\dcm2_flist.txt
..........\..........\dcm2_readme.txt
..........\..........\dcm2_xmdf.tcl
..........\..........\xaw2verilog.log
..........\.seconfig\dcm1.xreport
..........\.........\double_dcm.projectmgr
..........\modelsim.ini
..........\readme.txt
..........\top.v
..........\top_sim.fdo
..........\top_sim.udo
..........\top_sim.v
..........\top_sim_summary.html
..........\top_sim_wave.fdo
..........\transcript
..........\vsim.wlf
..........\work\dcm1\verilog.asm
..........\....\....\verilog.rw
..........\....\....\_primary.dat
..........\....\....\_primary.dbs
..........\....\....\_primary.vhd
..........\....\...2\verilog.asm
..........\....\....\verilog.rw
..........\....\....\_primary.dat
..........\....\....\_primary.dbs
..........\....\....\_primary.vhd
..........\....\glbl\verilog.asm
..........\....\....\verilog.rw
..........\....\....\_primary.dat
..........\....\....\_primary.dbs
..........\....\....\_primary.vhd
..........\....\top\verilog.asm
..........\....\...\verilog.rw
..........\....\...\_primary.dat
..........\....\...\_primary.dbs
..........\....\...\_primary.vhd
..........\....\..._sim\verilog.asm
..........\....\.......\verilog.rw
..........\....\.......\_primary.dat
..........\....\.......\_primary.dbs
..........\....\.......\_primary.vhd
..........\....\_info
..........\....\_vmake
..........\xaw2verilog.log
..........\_xmsgs\pn_parser.xmsgs
..........\ipcore_dir\tmp\_cg
..........\..........\tmp
..........\work\dcm1
..........\....\dcm2
..........\....\glbl
..........\....\top
..........\....\top_sim
..........\....\_temp
..........\ipcore_dir
..........\iseconfig
..........\work
..........\_xmsgs
double_dcm
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