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Title: example1 Download
 Description: Frequency program: to achieve a frequency of the clock signal clk is the function of
 Downloaders recently: [More information of uploader zhongqioubing]
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  • [9] - This article describes two kinds of sub-
  • [p-to-s] - Prepared using VHDL language and string
File list (Check if you may need any files):
example1\db\div.db_info
........\..\div.eco.cdb
........\..\div.sld_design_entry.sci
........\div.asm.rpt
........\div.done
........\div.dpf
........\div.fit.rpt
........\div.fit.smsg
........\div.fit.summary
........\div.flow.rpt
........\div.map.rpt
........\div.map.summary
........\div.pin
........\div.pof
........\div.qpf
........\div.qsf
........\div.qws
........\div.sim.rpt
........\div.tan.rpt
........\div.tan.summary
........\div.vhd
........\div.vwf
........\div_assignment_defaults.qdf
........\db
example1
    

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