Description: Verilog language used to write a simple shift register, can be arithmetic shift and logical shift.
To Search:
- [crack] - Altera Quartus II 10.1 latest crack file
- [I2C_Verilog_Model] - This source package is I2C bus model bas
File list (Check if you may need any files):
register\db\mux_3nc.tdf
........\..\prev_cmp_register.asm.qmsg
........\..\prev_cmp_register.fit.qmsg
........\..\prev_cmp_register.map.qmsg
........\..\prev_cmp_register.qmsg
........\..\prev_cmp_register.sim.qmsg
........\..\prev_cmp_register.tan.qmsg
........\..\register.asm.qmsg
........\..\register.asm_labs.ddb
........\..\register.atom.rvd
........\..\register.cbx.xml
........\..\register.cmp.bpm
........\..\register.cmp.cdb
........\..\register.cmp.ecobp
........\..\register.cmp.hdb
........\..\register.cmp.kpt
........\..\register.cmp.logdb
........\..\register.cmp.rdb
........\..\register.cmp.tdb
........\..\register.cmp0.ddb
........\..\register.cmp_merge.kpt
........\..\register.db_info
........\..\register.eco.cdb
........\..\register.eds_overflow
........\..\register.fit.qmsg
........\..\register.fnsim.hdb
........\..\register.fnsim.qmsg
........\..\register.hier_info
........\..\register.hif
........\..\register.lpc.html
........\..\register.lpc.rdb
........\..\register.lpc.txt
........\..\register.map.bpm
........\..\register.map.cdb
........\..\register.map.ecobp
........\..\register.map.hdb
........\..\register.map.kpt
........\..\register.map.logdb
........\..\register.map.qmsg
........\..\register.map_bb.cdb
........\..\register.map_bb.hdb
........\..\register.map_bb.logdb
........\..\register.pre_map.cdb
........\..\register.pre_map.hdb
........\..\register.rpp.qmsg
........\..\register.rtlv.hdb
........\..\register.rtlv_sg.cdb
........\..\register.rtlv_sg_swap.cdb
........\..\register.sgate.rvd
........\..\register.sgate_sm.rvd
........\..\register.sgdiff.cdb
........\..\register.sgdiff.hdb
........\..\register.sim.cvwf
........\..\register.sim.hdb
........\..\register.sim.qmsg
........\..\register.sim.rdb
........\..\register.simfam
........\..\register.sld_design_entry.sci
........\..\register.sld_design_entry_dsc.sci
........\..\register.syn_hier_info
........\..\register.tan.qmsg
........\..\register.tis_db_list.ddb
........\..\register.tmw_info
........\..\register_global_asgn_op.abo
........\..\wed.wsf
........\incremental_db\compiled_partitions\register.root_partition.cmp.atm
........\..............\...................\register.root_partition.cmp.dfp
........\..............\...................\register.root_partition.cmp.hdbx
........\..............\...................\register.root_partition.cmp.kpt
........\..............\...................\register.root_partition.cmp.logdb
........\..............\...................\register.root_partition.cmp.rcf
........\..............\...................\register.root_partition.map.atm
........\..............\...................\register.root_partition.map.dpi
........\..............\...................\register.root_partition.map.hdbx
........\..............\...................\register.root_partition.map.kpt
........\..............\README
........\register.dpf
........\register.qpf
........\register.qsf
........\register.qws
........\register.v
........\register.v.bak
........\register.vwf
........\..lease\register.asm.rpt
........\.......\register.done
........\.......\register.fit.rpt
........\.......\register.fit.smsg
........\.......\register.fit.summary
........\.......\register.flow.rpt
........\.......\register.map.rpt
........\.......\register.map.summary
........\.......\register.pin
........\.......\register.pof
........\.......\register.sim.rpt
........\.......\register.sof
........\.......\register.tan.rpt
........\.......\register.tan.summary
........\serv_req_info.txt
........\incremental_db\compiled_partitions
........\db
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