Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: sr8b Download
 Description: This is a shift register of 8bit It includes testbench It works DE2-70 board
 Downloaders recently: [More information of uploader freepcg]
 To Search:
  • [shift] - Simple shift register with testbench in
  • [shiftregister] - Shift Register. VHDL code and its testbe
File list (Check if you may need any files):
sr8b.asm.rpt
sr8b.cdf
sr8b.done
sr8b.dpf
sr8b.eda.rpt
sr8b.fit.rpt
sr8b.fit.summary
sr8b.flow.rpt
sr8b.map.rpt
sr8b.map.summary
sr8b.pin
sr8b.pof
sr8b.qpf
sr8b.qsf
sr8b.qsf.bak
sr8b.sof
sr8b.tan.rpt
sr8b.tan.summary
sr8b.v
sr8b.v.bak
sr8btb.v
sr8btb.v.bak
sr8b_nativelink_simulation.rpt
db\logic_util_heursitic.dat
..\prev_cmp_sr8b.qmsg
..\sr8b.amm.cdb
..\sr8b.asm.qmsg
..\sr8b.asm.rdb
..\sr8b.asm_labs.ddb
..\sr8b.cbx.xml
..\sr8b.cmp.bpm
..\sr8b.cmp.cbp
..\sr8b.cmp.cdb
..\sr8b.cmp.hdb
..\sr8b.cmp.kpt
..\sr8b.cmp.logdb
..\sr8b.cmp.rdb
..\sr8b.cmp.tdb
..\sr8b.cmp0.ddb
..\sr8b.cmp_merge.kpt
..\sr8b.db_info
..\sr8b.eda.qmsg
..\sr8b.fit.qmsg
..\sr8b.hier_info
..\sr8b.hif
..\sr8b.idb.cdb
..\sr8b.lpc.html
..\sr8b.lpc.rdb
..\sr8b.lpc.txt
..\sr8b.map.bpm
..\sr8b.map.cbp
..\sr8b.map.cdb
..\sr8b.map.hdb
..\sr8b.map.kpt
..\sr8b.map.logdb
..\sr8b.map.qmsg
..\sr8b.map_bb.cdb
..\sr8b.map_bb.hdb
..\sr8b.map_bb.logdb
..\sr8b.pre_map.cdb
..\sr8b.pre_map.hdb
..\sr8b.rtlv.hdb
..\sr8b.rtlv_sg.cdb
..\sr8b.rtlv_sg_swap.cdb
..\sr8b.sgdiff.cdb
..\sr8b.sgdiff.hdb
..\sr8b.sld_design_entry.sci
..\sr8b.sld_design_entry_dsc.sci
..\sr8b.smart_action.txt
..\sr8b.syn_hier_info
..\sr8b.tan.qmsg
..\sr8b.tis_db_list.ddb
..\sr8b.tmw_info
incremental_db\README
..............\compiled_partitions\sr8b.db_info
..............\...................\sr8b.root_partition.cmp.cdb
..............\...................\sr8b.root_partition.cmp.dfp
..............\...................\sr8b.root_partition.cmp.hdb
..............\...................\sr8b.root_partition.cmp.kpt
..............\...................\sr8b.root_partition.cmp.logdb
..............\...................\sr8b.root_partition.cmp.rcfdb
..............\...................\sr8b.root_partition.cmp.re.rcfdb
..............\...................\sr8b.root_partition.map.cdb
..............\...................\sr8b.root_partition.map.dpi
..............\...................\sr8b.root_partition.map.hdb
..............\...................\sr8b.root_partition.map.kpt
simulation\modelsim\modelsim.ini
..........\........\msim_transcript
..........\........\sr8b.sft
..........\........\sr8b.vo
..........\........\sr8b_modelsim.xrf
..........\........\sr8b_run_msim_rtl_verilog.do
..........\........\sr8b_run_msim_rtl_verilog.do.bak
..........\........\sr8b_run_msim_rtl_verilog.do.bak1
..........\........\sr8b_run_msim_rtl_verilog.do.bak10
..........\........\sr8b_run_msim_rtl_verilog.do.bak11
..........\........\sr8b_run_msim_rtl_verilog.do.bak2
..........\........\sr8b_run_msim_rtl_verilog.do.bak3
..........\........\sr8b_run_msim_rtl_verilog.do.bak4
..........\........\sr8b_run_msim_rtl_verilog.do.bak5
    

CodeBus www.codebus.net