risc8\alu.v
.....\basic.rom
.....\chart\图13-11.bmp
.....\.....\图13-13.bmp
.....\.....\图13-15.bmp
.....\.....\图13-16.bmp
.....\.....\图13-17.bmp
.....\.....\图13-18.bmp
.....\.....\图13-20.bmp
.....\.....\图13-6.bmp
.....\.....\图13-7.bmp
.....\.....\图13-9.bmp
.....\.....\表13-1.bmp
.....\cpu.v
.....\cpu_test.v
.....\dram.v
.....\exp.v
.....\idec.v
.....\pram.v
.....\regs.v
.....\risc8.cr.mti
.....\risc8.mpf
.....\risc8.vcd
.....\sindata.hex
.....\transcript
.....\vsim.wlf
.....\wave\alu.bmp
.....\....\cpu-1.bmp
.....\....\cpu-2.bmp
.....\....\cpu_test.bmp
.....\....\exp.bmp
.....\....\idec.bmp
.....\....\pram.bmp
.....\....\regs.bmp
.....\.ork\alu\verilog.asm
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\cpu\verilog.asm
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\..._test\verilog.asm
.....\....\........\_primary.dat
.....\....\........\_primary.vhd
.....\....\dram\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\exp\verilog.asm
.....\....\...\_primary.dat
.....\....\...\_primary.vhd
.....\....\idec\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\pram\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\regs\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\risc8.vcd
.....\....\test\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\_info
.....\....\alu
.....\....\cpu
.....\....\cpu_test
.....\....\dram
.....\....\exp
.....\....\idec
.....\....\pram
.....\....\regs
.....\....\test
.....\chart
.....\wave
.....\work
risc8