test
....\readme.txt
doc
...\nova_spec.doc
...\readme.txt
MISC
....\readme.txt
src
...\Beha_BitStream_ram.v
...\BitStream_buffer.v
...\BitStream_controller.v
...\bitstream_gclk_gen.v
...\BitStream_parser_FSM_gating.v
...\bs_decoding.v
...\cavlc_consumed_bits_decoding.v
...\cavlc_decoder.v
...\CodedBlockPattern_decoding.v
...\dependent_variable_decoding.v
...\DF_mem_ctrl.v
...\DF_pipeline.v
...\DF_reg_ctrl.v
...\DF_top.v
...\end_of_blk_decoding.v
...\exp_golomb_decoding.v
...\ext_frame_RAM0_wrapper.v
...\ext_frame_RAM1_wrapper.v
...\ext_RAM_ctrl.v
...\heading_one_detector.v
...\hybrid_pipeline_ctrl.v
...\Inter_mv_decoding.v
...\Inter_pred_CPE.v
...\Inter_pred_LPE.v
...\Inter_pred_pipeline.v
...\Inter_pred_reg_ctrl.v
...\Inter_pred_sliding_window.v
...\Inter_pred_top.v
...\Intra4x4_PredMode_decoding.v
...\Intra_pred_PE.v
...\Intra_pred_pipeline.v
...\Intra_pred_reg_ctrl.v
...\Intra_pred_top.v
...\IQIT.v
...\level_decoding.v
...\nC_decoding.v
...\nova.v
...\nova_defines.v
...\nova_tb.v
...\NumCoeffTrailingOnes_decoding.v
...\pc_decoding.v
...\QP_decoding.v
...\ram_async_1r_sync_1w.v
...\ram_sync_1r_sync_1w.v
...\reconstruction.v
...\rec_DF_RAM0_96x32.v
...\rec_DF_RAM0_wrapper.v
...\rec_DF_RAM1_96x32.v
...\rec_DF_RAM1_wrapper.v
...\rec_DF_RAM_ctrl.v
...\rec_gclk_gen.v
...\run_decoding.v
...\sum.v
...\syntax_decoding.v
...\timescale.v
...\total_zeros_decoding.v