Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: 7segment Download
 Description: it is 7 segement code
 To Search:
File list (Check if you may need any files):
7segment\.lso
........\7segment.ise
........\7segment.ise_ISE_Backup
........\7segment.ntrc_log
........\7segment.restore
........\7_segment_display.vhd
........\7_segment_display_summary.html
........\device_usage_statistics.html
........\seg.ucf
........\seg7.bgn
........\seg7.bit
........\SEG7.bld
........\SEG7.cmd_log
........\seg7.drc
........\SEG7.lso
........\SEG7.mfp
........\SEG7.ncd
........\SEG7.ngc
........\SEG7.ngd
........\SEG7.ngr
........\SEG7.pad
........\SEG7.par
........\SEG7.pcf
........\SEG7.prj
........\SEG7.stx
........\SEG7.syr
........\seg7.twr
........\seg7.twx
........\SEG7.unroutes
........\SEG7.ut
........\SEG7.xpi
........\SEG7.xst
........\SEG7_fpga_editor.log
........\SEG7_fpga_editor.out
........\SEG7_guide.ncd
........\SEG7_map.map
........\SEG7_map.mrp
........\SEG7_map.ncd
........\SEG7_map.ngm
........\SEG7_pad.csv
........\SEG7_pad.txt
........\SEG7_prev_built.ngd
........\SEG7_summary.html
........\SEG7_summary.xml
........\SEG7_usage.xml
........\SEG7_vhdl.prj
........\xst\dump.xst\SEG7.prj\ntrc.scr
........\...\work\hdllib.ref
........\...\....\hdpdeps.ref
........\...\....\sub00\vhpl00.vho
........\...\....\.....\vhpl01.vho
........\_ngo\netlist.lst
........\.xmsgs\bitgen.xmsgs
........\......\map.xmsgs
........\......\ngdbuild.xmsgs
........\......\par.xmsgs
........\......\trce.xmsgs
........\......\xst.xmsgs
........\xst\dump.xst\SEG7.prj\ngx\notopt
........\...\........\........\...\opt
........\...\........\........\ngx
........\...\........\SEG7.prj
........\...\work\sub00
........\...\dump.xst
........\...\projnav.tmp
........\...\work
........\xst
........\_ngo
........\_xmsgs
7segment
    

CodeBus www.codebus.net