Description: This is a description using VHDL, 8-line-3 line decoder, we want to be useful
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File list (Check if you may need any files):
coder1\coder1.done
......\coder1.flow.rpt
......\coder1.map.rpt
......\coder1.map.summary
......\coder1.qpf
......\coder1.qsf
......\coder1.qws
......\coder1.vhd
......\coder1.vhd.bak
......\db\coder1.cbx.xml
......\..\coder1.cmp.rdb
......\..\coder1.cmp_merge.kpt
......\..\coder1.db_info
......\..\coder1.eco.cdb
......\..\coder1.hier_info
......\..\coder1.hif
......\..\coder1.map.bpm
......\..\coder1.map.cdb
......\..\coder1.map.ecobp
......\..\coder1.map.hdb
......\..\coder1.map.kpt
......\..\coder1.map.logdb
......\..\coder1.map.qmsg
......\..\coder1.map_bb.cdb
......\..\coder1.map_bb.hdb
......\..\coder1.map_bb.hdbx
......\..\coder1.map_bb.logdb
......\..\coder1.pre_map.cdb
......\..\coder1.pre_map.hdb
......\..\coder1.psp
......\..\coder1.rtlv.hdb
......\..\coder1.rtlv_sg.cdb
......\..\coder1.rtlv_sg_swap.cdb
......\..\coder1.sgdiff.cdb
......\..\coder1.sgdiff.hdb
......\..\coder1.sld_design_entry.sci
......\..\coder1.sld_design_entry_dsc.sci
......\..\coder1.syn_hier_info
......\..\coder1.tis_db_list.ddb
......\..\coder1.tmw_info
......\..\prev_cmp_coder1.map.qmsg
......\..\prev_cmp_coder1.qmsg
......\incremental_db\compiled_partitions\coder1.root_partition.map.atm
......\..............\...................\coder1.root_partition.map.dpi
......\..............\...................\coder1.root_partition.map.hdbx
......\..............\...................\coder1.root_partition.map.kpt
......\..............\README
......\..............\compiled_partitions
......\db
......\incremental_db
coder1
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