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Title: dct01 Download
 Description: Verilog serial communication prepared under the decoder state machine
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File list (Check if you may need any files):
serial.bdf
UART_RX.asm.rpt
UART_RX.bsf
UART_RX.done
UART_RX.dpf
UART_RX.fit.rpt
UART_RX.fit.smsg
UART_RX.fit.summary
UART_RX.flow.rpt
UART_RX.jed
UART_RX.map.rpt
UART_RX.map.summary
UART_RX.pin
UART_RX.pof
UART_RX.qpf
UART_RX.qsf
UART_RX.qws
UART_RX.sof
UART_RX.tan.rpt
UART_RX.tan.summary
UART_RX.txt
UART_RX.v
UART_RX.v.bak
UART_RX_assignment_defaults.qdf
db\logic_util_heursitic.dat
..\prev_cmp_UART_RX.asm.qmsg
..\prev_cmp_UART_RX.fit.qmsg
..\prev_cmp_UART_RX.map.qmsg
..\prev_cmp_UART_RX.qmsg
..\prev_cmp_UART_RX.tan.qmsg
..\UART_RX.asm.qmsg
..\UART_RX.asm.rdb
..\UART_RX.cbx.xml
..\UART_RX.cmp.cdb
..\UART_RX.cmp.hdb
..\UART_RX.cmp.kpt
..\UART_RX.cmp.logdb
..\UART_RX.cmp.rdb
..\UART_RX.cmp0.ddb
..\UART_RX.db_info
..\UART_RX.eco.cdb
..\UART_RX.fit.qmsg
..\UART_RX.hier_info
..\UART_RX.hif
..\UART_RX.lpc.html
..\UART_RX.lpc.rdb
..\UART_RX.lpc.txt
..\UART_RX.map.cdb
..\UART_RX.map.hdb
..\UART_RX.map.logdb
..\UART_RX.map.qmsg
..\UART_RX.pre_map.cdb
..\UART_RX.pre_map.hdb
..\UART_RX.rtlv.hdb
..\UART_RX.rtlv_sg.cdb
..\UART_RX.rtlv_sg_swap.cdb
..\UART_RX.sgdiff.cdb
..\UART_RX.sgdiff.hdb
..\UART_RX.sld_design_entry.sci
..\UART_RX.sld_design_entry_dsc.sci
..\UART_RX.smart_action.txt
..\UART_RX.smp_dump.txt
..\UART_RX.syn_hier_info
..\UART_RX.tis_db_list.ddb
..\UART_RX.tmw_info
incremental_db\compiled_partitions\UART_RX.root_partition.map.kpt
..............\README
dct01.bsf
dct01.v
jtag.log
incremental_db\compiled_partitions
db
incremental_db
    

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