Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: jicun Download
 Description: module registers071221049 ( input [4:0]s1,s2, input [4:0] wd, input [31:0] data, input wre, clk, input he,hc,le,lc, output [31:0] out1, output [31:0] out2 )
 Downloaders recently: [More information of uploader jstztxjf]
 To Search:
File list (Check if you may need any files):
jicun.txt
    

CodeBus www.codebus.net