Description: Register realization of the principle, 16, Verilog language, the simulation successfully.
To Search:
File list (Check if you may need any files):
Reg16
.....\db
.....\..\prev_cmp_Reg16_071221139.asm.qmsg
.....\..\prev_cmp_Reg16_071221139.fit.qmsg
.....\..\prev_cmp_Reg16_071221139.map.qmsg
.....\..\prev_cmp_Reg16_071221139.qmsg
.....\..\prev_cmp_Reg16_071221139.tan.qmsg
.....\..\Reg16_071221139.cbx.xml
.....\..\Reg16_071221139.cmp.rdb
.....\..\Reg16_071221139.cmp_merge.kpt
.....\..\Reg16_071221139.db_info
.....\..\Reg16_071221139.eco.cdb
.....\..\Reg16_071221139.hier_info
.....\..\Reg16_071221139.hif
.....\..\Reg16_071221139.lpc.html
.....\..\Reg16_071221139.lpc.rdb
.....\..\Reg16_071221139.lpc.txt
.....\..\Reg16_071221139.map.bpm
.....\..\Reg16_071221139.map.cdb
.....\..\Reg16_071221139.map.ecobp
.....\..\Reg16_071221139.map.hdb
.....\..\Reg16_071221139.map.kpt
.....\..\Reg16_071221139.map.logdb
.....\..\Reg16_071221139.map.qmsg
.....\..\Reg16_071221139.map_bb.cdb
.....\..\Reg16_071221139.map_bb.hdb
.....\..\Reg16_071221139.map_bb.logdb
.....\..\Reg16_071221139.pre_map.cdb
.....\..\Reg16_071221139.pre_map.hdb
.....\..\Reg16_071221139.rtlv.hdb
.....\..\Reg16_071221139.rtlv_sg.cdb
.....\..\Reg16_071221139.rtlv_sg_swap.cdb
.....\..\Reg16_071221139.sgdiff.cdb
.....\..\Reg16_071221139.sgdiff.hdb
.....\..\Reg16_071221139.sld_design_entry.sci
.....\..\Reg16_071221139.sld_design_entry_dsc.sci
.....\..\Reg16_071221139.syn_hier_info
.....\..\Reg16_071221139.tis_db_list.ddb
.....\..\Reg16_071221139.tmw_info
.....\incremental_db
.....\..............\compiled_partitions
.....\..............\...................\Reg16_071221139.root_partition.map.atm
.....\..............\...................\Reg16_071221139.root_partition.map.dpi
.....\..............\...................\Reg16_071221139.root_partition.map.hdbx
.....\..............\...................\Reg16_071221139.root_partition.map.kpt
.....\..............\README
.....\Reg16_071221139.dpf
.....\Reg16_071221139.qpf
.....\Reg16_071221139.qsf
.....\Reg16_071221139.qsf.bak
.....\Reg16_071221139.qws
.....\Reg16_071221139.v
.....\Reg16_071221139.v.bak
.....\Reg16_071221139_assignment_defaults.qdf
.....\release
.....\.......\Reg16_071221139.asm.rpt
.....\.......\Reg16_071221139.done
.....\.......\Reg16_071221139.fit.rpt
.....\.......\Reg16_071221139.fit.smsg
.....\.......\Reg16_071221139.fit.summary
.....\.......\Reg16_071221139.flow.rpt
.....\.......\Reg16_071221139.map.rpt
.....\.......\Reg16_071221139.map.smsg
.....\.......\Reg16_071221139.map.summary
.....\.......\Reg16_071221139.pin
.....\.......\Reg16_071221139.pof
.....\.......\Reg16_071221139.sof
.....\.......\Reg16_071221139.tan.rpt
.....\.......\Reg16_071221139.tan.summary
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