Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: zhuantaiji Download
 Description: Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequences, finite state machines provide a total of eight states (including the initial state IDLE).
 Downloaders recently: [More information of uploader cherry033]
 To Search:
  • [USE_FSM_DEDIGN_SRAM] - With the FSM (finite state machine) desi
  • [fsm] - VHDL Getting Started: Finite state machi
File list (Check if you may need any files):
zhuantaiji.txt
    

CodeBus www.codebus.net