uart_tb.v.bak
uart_tb.vcd
vsim.wlf
rtl_wrk\@rx\verilog.asm
.......\...\_primary.dat
.......\...\_primary.vhd
.......\.tx\verilog.asm
.......\...\_primary.dat
.......\...\_primary.vhd
.......\uart_tb\verilog.asm
.......\.......\_primary.dat
.......\.......\_primary.vhd
.......\_info
modelsim.ini
run.do
Rx.v
Rx.v.bak
Tx.v
Tx.v.bak
uart_tb.v
rtl_wrk\@rx
.......\@tx
.......\uart_tb
rtl_wrk